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Vivado 2018.1 non-project DDR4 IP intergration.

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Visitor
Posts: 13
Registered: ‎11-13-2017

Vivado 2018.1 non-project DDR4 IP intergration.

Hi.

 

Nowdays, I am building tcl script on the non-project base. But one thing makes me crazy.

 

that is DDR4 Xilinx IP. 

 

I use the VCU1525 development kit and vivado 2018.1.

 

vivado tool works well by "generate_target" command.

 

while synthesis the module, vivado tool send message to me "generated XDC of IP path is wrong"

 

but when I build tcl script on project base, all things is fine.

 

Is there anyone who share non-project script? 

 

please help me.

 

 

Moderator
Posts: 960
Registered: ‎09-15-2016

Re: Vivado 2018.1 non-project DDR4 IP intergration.

Hi @uramashi2

 

Refer  below link for scripting in non-project flow using IP, Chapter 4. Hope it helps:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug939-vivado-designing-with-ip-tutorial.pdf

Regards
Rohit
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Moderator
Posts: 2,155
Registered: ‎01-16-2013

Re: Vivado 2018.1 non-project DDR4 IP intergration.

@uramashi2

 

Can you share the complete message? 

Chapter 4 in below UG covers the non-project mode with example:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug892-vivado-design-flows-overview.pdf

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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