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embedded
Advisor
Advisor
754 Views
Registered: ‎06-09-2011

Vivado 2020.1 does not run tcl commands

Hi all,

I have used write_project_tcl to create a tcl file for future use in Git version control. It is a Block Design project for ZCU104 board. You see highlighted connections in reference project that Vivado forgets them during project creation.

 

These are commands of generated tcl file:

connect_bd_net -net axis_dwidth_converter_0_m_axis_tid [get_bd_pins axis_data_fifo_0/s_axis_tuser] [get_bd_pins axis_dwidth_converter_0/m_axis_tid]
connect_bd_net -net xlconstant_0_dout [get_bd_pins axis_data_fifo_0/s_axis_tid] [get_bd_pins xlconstant_0/dout]
connect_bd_net -net axis_switch_0_m_axis_tuser [get_bd_pins axis_dwidth_converter_0/s_axis_tid] [get_bd_pins axis_switch_0/m_axis_tuser]

 However, after project creation I see it has forgotten to connect these connections and I am worried if it maybe forget further connection, settings etc?

 

 I have also tried wrtie_project_tcl with some other arguments like: -all_properties

However, it did not work.

I woudl appreciate any help.

Thanks,
Hossein
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ashishd
Xilinx Employee
Xilinx Employee
739 Views
Registered: ‎02-14-2014

Hi @embedded ,

Are there any warnings / critical warnings while running script generated using write_project_tcl / write_bd_tcl ?

Is it possible for you to share original project ?

Regards,
Ashish
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olupj
Explorer
Explorer
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Registered: ‎01-27-2008

@embedded 

I've been able to use write_bd_tcl for block diagrams with decent success and even check that in (using Git), reproducing a subset of the design reliably.

I use the -include_layout command and ensure a wrapper is generated when doing so.

Not sure if write_project_tcl is similar for a block design.

However if you proceed with write_project_tcl you should include the -verbose flag to assist in revealing any strange behavior.

Have fun,

Jerry

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embedded
Advisor
Advisor
661 Views
Registered: ‎06-09-2011

Hi @olupj ,

Thanks for your comments and hints. However, I don't think if these two commands - write_project_tcl and write_bd_tcl - have any differences in creating BD. I can see that there are commands in the tcl file for connecting those pins together.

connect_bd_net -net axis_dwidth_converter_0_m_axis_tid [get_bd_pins axis_data_fifo_0/s_axis_tuser] [get_bd_pins axis_dwidth_converter_0/m_axis_tid]
connect_bd_net -net xlconstant_0_dout [get_bd_pins axis_data_fifo_0/s_axis_tid] [get_bd_pins xlconstant_0/dout]
connect_bd_net -net axis_switch_0_m_axis_tuser [get_bd_pins axis_dwidth_converter_0/s_axis_tid] [get_bd_pins axis_switch_0/m_axis_tuser]

I don't know why - for any reason - Vivado doesn't run them during recreation of the project? And, if I run them manually after creation it connects them. I also enabled verbose switch during write_project_tcl command. I did not see any error or warning messages.

Could you please tell me how I can use output file of write_bd_tcl?

I appreciate your help.

 

Thanks,
Hossein
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embedded
Advisor
Advisor
659 Views
Registered: ‎06-09-2011

Hi @ashishd,

No error or warning messages.

Thanks,
Hossein
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olupj
Explorer
Explorer
626 Views
Registered: ‎01-27-2008

Hi @embedded 

I use the output of

 

write_bd_tcl -bd_name your_name -include_layout -force -verbose ./pathto/make_named_bd.tcl

 

Directly in my project build script calling it with

 

source -notrace ./pathto/make_named_bd.tcl

 

From my project tcl script. That makes a bd that is easily maintained in Git or SVN.

If you use write_project_tcl and your bd is part of larger design, but you want to isolate and target bd generation, you probably want to use write_bd_tcl rather than write_project_tcl.

I do see how write_project_tcl includes the bd, but like to separate the bd from the top level code, which is often RTL tying multiple block diagrams together.

Does that help?

Jerry

embedded
Advisor
Advisor
545 Views
Registered: ‎06-09-2011

Hi @olupj,

Thank you for your answer. I do not have any tcl file for creating project except to that one I use write_project_tcl. This one contains al information in a unique file. Is there any reference that shows how I can created a project using this method? I mean one specific tcl file for creating BD and also some other commands for the rest of design.

 

Thanks,
Hossein
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embedded
Advisor
Advisor
541 Views
Registered: ‎06-09-2011

Hi @olupj,

Unfortunately, I get some errors when I run the tcl file with your suggested command.

source -notrace ./pathto/make_named_bd.tcl

This creates below errors:

NFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hossein/tools/Xilinx/Vivado/2020.1/data/ip'.
INFO: [BD::TCL 103-2003] Currently there is no design <zcu102_es2_base_trd.bd> in project, so creating one...
Wrote  : </home/hossein/Embedded/Remote/exmp/myproj/project_1.srcs/sources_1/bd/zcu102_es2_base_trd/zcu102_es2_base_trd.bd> 
INFO: [BD::TCL 103-2004] Making design <zcu102_es2_base_trd.bd> as current_bd_design.
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 Could you please be more specific and mention how this tcl file can be used?

 

Thanks,
Hossein
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olupj
Explorer
Explorer
530 Views
Registered: ‎01-27-2008

Hi @embedded  (Hossein)

Sorry missed this earlier.

>>I do not have any tcl file for creating project except to that one I use write_project_tcl.

I referred to your original post since we're a little into the thread. 

So I did a similar thing to you with the top level block diagram.

You validated your block diagram?

validate_bd_design

Then, having the bd open, you should be able to use the above write_bd_tcl command to capture the block diagram in a TCL script.

I am not certain what you mean when you say you do not have any tcl file for creating project except ... but your following statement:

>>Is there any reference that shows how I can created a project using this method? I mean one specific tcl file for creating BD and also some other commands for the rest of design.

what I do is use the write_bd_tcl command as shown above and then integrate into a larger (hand made) build script that captures the larger project space.

When I say "integrate into larger build script" I mean something like this:

# ip from quad_downconverter, skip rfdc used for sim
# add_files [glob ../quad_downconv/ip/hb_filt_stage*.xci]
# add_files [glob ../quad_downconv/ip/cmplx_mult_*.xci]

# block diagram
set p_bd "./scripts/make_some_dma_bd.tcl"
source -notrace $p_bd
make_wrapper -files [get_files $relpath$p_default/some_build.srcs/sources_1/bd/some_dma/some_dma.bd] -top
add_files -norecurse $relpath$p_default/some_build.srcs/sources_1/bd/some_dma/hdl/some_dma_wrapper.v
# wrapper
# add_files [glob ../../../viv_projects/test_design/test_design.srcs/sources_1/imports/hdl/some_dma_wrapper.v]

So once I created make_some_dma_bd.tcl, in the project GUI, with the appropriate bd open, I can integrate that script into other scripts through the source -notrace make_some_dma_bd.tcl function.

I am not sure of your error but you can check your script for all

'set_property'

lines and find the error. At least I think you'll be able to. You might also validate the bd and make sure the original connectivity issues don't show up. I've seen this happen before and it might show you any issues (as @ashishd mentioned).

So for the bd diagram I let xilinx generate it but generally I do not use the products (which are noisy and not easy to maintain and extend) generated from write_project_tcl.

As mentioned it's really noisy and not very scalable, so I would ignore it and write your own build script. However, I encourage integration of the product of write_bd_tcl to encapsulate the block diagram.

 

I hope this helps,

Jerry

 

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embedded
Advisor
Advisor
482 Views
Registered: ‎06-09-2011

Hi @olupj

Thank you for the detailed information. I found a way to use bd.tcl file - I am new to tcl scripting - by modifying some available reference design tcl scripts from Xilinx. However, Vivado persists on the same problem of not connecting those specific AXI pins. Just like the tcl file of write_project_tcl, your suggested method - write_bd_tcl - contains the necessary commands for connecting those AXI pins. If you run the tcl, Vivado ignores those commands.

 

Thanks,
Hossein
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olupj
Explorer
Explorer
464 Views
Registered: ‎01-27-2008

Hi Hossein ( @embedded )

Are the pins connected in the block diagram, but yet, fail to connect through write_project_tcl or write_bd_tcl?

I would think that is unusual.

validate_bd_design passes without warnings on errors on those connections?

So let's dive a little more into the TCL world.

You're using connect_bd_net from pin to pin in the block diagram.

I have not had to do this but it should work. Try this:

foreach a [get_bd_nets] { puts $a }

  • That will list all block diagram nets

Then do the same with bd pins

foreach a [get_bd_pins] { puts $a }

  • That lists all pins

These can be large so cut them to a file for easier viewing than the console.

If the pins are there you should be able to connect them.

That is, if properties match. So I played around a bit while building and couldn't get the

However if your ran connect_bd_net manually and the tool didn't like it, I would expect some warnings.

Maybe run with connect_bd_net -verbose.

Generally you don't need a net name (it's optional).

 

Forced into doing this, you will quickly develop expertise.

Jerry

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