01-07-2020 07:10 AM
I have a Python flow where I wish to integrate programming of the Artix FPGA using the Xilinx JTAG Programmer. What could work is having an instance of Vivado running in the backgroung, and having Python call tcl commands at runtime to open hardware, connect to it and then fully / partially reconfigure it depending on the underlying logic. Is there a way to do this?
02-03-2020 12:41 AM
Can you elaborate on the point - "having Python call tcl commands at runtime to open hardware"?
Are you looking for tcl commands for it?
02-03-2020 01:34 AM
02-03-2020 04:32 AM
The situation is that I have a Python script which need to reconfigure the FPGA repeatedly. Currently I am using Vivado in batch mode with a TCL script which will open the Hardware Manager and program the FPGA using the bitstream file which is passed as a parameter to the TCL script. Problem here is that each time Vivado is started and shut down, and also the hardware manager is started, which takes a lot of time. If Vivado could remain running in the background and I could just run commands to program the FPGA (on that specific instance of VIvado), it would save a lot of runtime.
02-03-2020 05:29 AM
02-03-2020 05:41 AM
Thanks a lot for the suggestion, but the Python workflow is handling many other things apart form the FPGA reconfiguration, and hence it is essential that the control remains with the Python tool. Besides, the Python tool is interactive (using a Jupyter frontend).
Assuming that I somehow invoke the Jupyter notebook and Python backend from Vivado (exec), could you please elaborate how the Python should reconfigure the FPGA? Currently I invoke a .sh file with parameters, which in turn starts vivado (./vivado) in batch mode with the .tcl file as a paramerter. As I understand, by invoking my Python flow from Vivado, it would likely open another instance of Vivado and behave just as it is behaving now.
02-03-2020 05:49 AM