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Observer pablo_trujillo
Observer
1,942 Views
Registered: ‎02-02-2017

Vivado IP ERROR non-pproject mode

Hello all,

I have a script for generate release files of verilog project. I have several projects, with IP or not. In projects with some IP, untl now, sometimes vivado trips an error, but now I can't run the script because all times trips error. If I create a project in vivado, all works fine.

script:

file mkdir $outputDir/report

file delete [ glob vivado_*.backup.jou]
file delete [ glob vivado_*.backup.log]

## Read verilog files
read_verilog [ glob ../source/*.v]
##read_vhdl [ glob ../source/*.vhd]

set_part $part_name
## Read ip files
read_ip ../ip/div_gen_0.xci
generate_target all [get_files div_gen_0.xci] -force
synth_ip [ get_ips div_gen_0] -force

## Read memory files
read_mem [ glob ../memory_code/*.mem]

## Read constraints file
read_xdc ../constraints/E973Bx.xdc

## Synthesis
synth_design -part $part_name -top top_hemk -include_dirs ../include
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/report/post_synth_timing_summary.rpt
report_power -file $outputDir/report/post_synth_power.rpt

Vivado log:

# generate_target all [get_files div_gen_0.xci] -force
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'div_gen_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'div_gen_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'div_gen_0'...
CRITICAL WARNING: [IP_Flow 19-157] Failed to copy file from 'c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mult_gen_v12_0/hdl/mult_gen_v12_0_vh_rfs.vhd' to 'c:/Users/ptrujillo/git/verilog/hemk_module/ip/hdl/mult_gen_v12_0_vh_rfs.vhd'.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'div_gen_0'. Failed to generate 'VHDL Simulation' outputs: 
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'div_gen_0'. Failed to generate 'VHDL Simulation' outputs: 
Vivado% 

I don't know why vivado can't copy these files... In IP folder, I have only one file, div_gen0.xci. Thanks in advance!

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4 Replies
Xilinx Employee
Xilinx Employee
1,933 Views
Registered: ‎08-01-2008

Re: Vivado IP ERROR non-pproject mode

rom the warning message, it seems like you are missing div_gen_0.v file while creating the IP.

Make sure you add the div_gen_.v file in File groups while packaging the IP. See below snapshot: 

ip_packager.PNG

 You may follow the steps in Vivado GUI and generate the script . 

 

Hope it may help you

Thanks and Regards
Balkrishan
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Observer pablo_trujillo
Observer
1,778 Views
Registered: ‎02-02-2017

Re: Vivado IP ERROR non-pproject mode

Hello balkris!,

with christmas holidays I forgot answer this post!, sorry!!. In home, I tried to sintesize the same code with same files and it works fine, maybe can be problem with windows permissions?. The IP I've talk is a vivado IP, no a own IP... I remember to read in any web that only is necessary to add a project a .xci file of Xilinx IP... is that correct?

In your snapshot, you show a file Groups, but this windows is not in my vivado... how can I arrive to this window?

 

Thank you!

 

greetings!

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Moderator
Moderator
1,742 Views
Registered: ‎09-15-2016

Re: Vivado IP ERROR non-pproject mode

Hi @pablo_trujillo,

 

Yes, only .xci file is needed. But we see the tool having issues copying the simulation files for generating simulation target. You can try to use this IP separately in project mode and generate, synthesize the IP to check for issues. Try the same path.

 

As you said the same script worked for another machine, this might be an issue with permission for the below path.

 

c:/Users/ptrujillo/git/

 

For information, the file groups section is in 'Edit in IP Packager' section. (Reference UG1118 Page no. 49)

 

Regards,
Prathik
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Observer pablo_trujillo
Observer
1,331 Views
Registered: ‎02-02-2017

Re: Vivado IP ERROR non-project mode

Hello all,

I've found the error!. During these months the error rises up randomly in 30% (more or less), of my synthesis. Recently, I've deleted from git all temporal files generated by vivado, This includes all ip files except .xci and the error never rise up again. I think git update this files, and for that, git open file at same time than vivado wants to do the same. Sorry for late answer!!

Thanks!!

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