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Adventurer
Adventurer
16,106 Views
Registered: ‎11-04-2010

Vivado TCL script to insert ILA

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This script will insert ILAs into your design, post-synthesis, in non-project mode. You need to constrain desired nets in your Verilog RTL with: (* keep="true",mark_debug="true" *). The script will find these nets and attach them to an ILA, with the correct clock, trying to keep buses intact.

 

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Scholar jmcclusk
Scholar
23,366 Views
Registered: ‎02-24-2014

Re: Vivado TCL script to insert ILA

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Here is a seriously improved version of the TCL batch insertion script.   This handles the problem of uncertain or unknown clock domains by adding a user defined attribute "mark_debug_clock" that allows directly specifying the clock net to use for capturing the signal in question.   Depth of the ILA core can be specified via "mark_debug_depth",   and advanced triggering is supported with the attribute "mark_debug_adv_trigger".     Nets that are attached to VIO cores are rejected, unless marked with "mark_debug_valid".   Finally, when more than 1 ILA core is created,  the trigger inputs and outputs are connected in a circle, so that triggering in one ILA core can be used to trigger all the remaining cores.   This is a function that doesn't seem to be available in the Vivado GUI "setup debug".    I've also added a bit of code at the end to save constraints if it detects that the script is invoked from the GUI, so it should also be useable (with a wrapper) as a post synth TCL script.   I'm sure there are things still to be improved, but this is a major step forward.

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15 Replies
Xilinx Employee
Xilinx Employee
16,036 Views
Registered: ‎10-24-2013

Re: Vivado TCL script to insert ILA

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Thanks for the script. This will serve as a reference to the other users.
Thanks,Vijay
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Scholar jmcclusk
Scholar
15,902 Views
Registered: ‎02-24-2014

Re: Vivado TCL script to insert ILA

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Thanks for the script, vertreko.    In my design, I had a problem with your script connecting the ILA clock to the upstream side of the clock buffer, so  I've modified your script to choose clock nets more locally, searching for a clock net attached to the driver cell of the debug net first, and then using the startpoint_pin of the timing path if that fails.    The question of which clock to use for capturing a debug net is a subtle one, since cross clock domain paths have 2 choices, and nets driven by input buffers can have zero to many choices.     We really need an expansion of the "mark_debug" attribute system, to allow specification of the capture clock to be selected for a debug net.    Yet another feature we could use is a way to specify the ILA properties, such as depth, input pipelining, advanced trigger, etc...    I've added ILA depth as an input parameter to the procedure, but it's a very blunt hammer, since all ILA cores will have the same depth. 

 

By the way,  for those using manual ILA insertion in the GUI with "implement_debug_cores", which forces a save (and rewrite) of the constraint files,  I've been told that the upcoming 2014.1 release may relax this requirement.    I'm also hoping that 2014.1 will have a simpler way to implement automatic refresh on ILA capture...    When I write a loop to trigger and display the ILA waveform, it tends to crash after a short while (in 2013.4)

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Scholar jmcclusk
Scholar
23,367 Views
Registered: ‎02-24-2014

Re: Vivado TCL script to insert ILA

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Here is a seriously improved version of the TCL batch insertion script.   This handles the problem of uncertain or unknown clock domains by adding a user defined attribute "mark_debug_clock" that allows directly specifying the clock net to use for capturing the signal in question.   Depth of the ILA core can be specified via "mark_debug_depth",   and advanced triggering is supported with the attribute "mark_debug_adv_trigger".     Nets that are attached to VIO cores are rejected, unless marked with "mark_debug_valid".   Finally, when more than 1 ILA core is created,  the trigger inputs and outputs are connected in a circle, so that triggering in one ILA core can be used to trigger all the remaining cores.   This is a function that doesn't seem to be available in the Vivado GUI "setup debug".    I've also added a bit of code at the end to save constraints if it detects that the script is invoked from the GUI, so it should also be useable (with a wrapper) as a post synth TCL script.   I'm sure there are things still to be improved, but this is a major step forward.

Don't forget to close a thread when possible by accepting a post as a solution.
Moderator
Moderator
12,950 Views
Registered: ‎07-01-2015

Re: Vivado TCL script to insert ILA

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Hi @jmcclusk, @vertreko,

 

Thanks for sharing the Tcl file for ILA.

@vertreko please close the thread by marking answer as "Accept as solution". It will be helpful for other users to search easily for Tcl file for ILA.

 

Thanks,
Arpan

 

Thanks,
Arpan
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Observer jamey.hicks
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12,733 Views
Registered: ‎05-02-2014

Re: Vivado TCL script to insert ILA

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@jmcclusk Thanks for posting this script! It works really well, and I've been sharing it with other people I know using Vivado.

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Observer soma_yow
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3,583 Views
Registered: ‎05-01-2017

Re: Vivado TCL script to insert ILA

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Any tips on how to use this with a project flow? I can get it to run between the synth and impl flow, but the debug cores don't get picked up by the implementation. I think I need to somehow add the debug_cores.xdc file to the impl constraint set somehow.

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Scholar jmcclusk
Scholar
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Registered: ‎02-24-2014

Re: Vivado TCL script to insert ILA

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This may need updating to work with newer versions of Vivado.   What version are you using?

 

One problem that I've seen is that the debug hub needs a free running clock, and Vivado will sometimes connect the free running clock on the hub to a clock in the design that's randomly picked (apparently).   This will fail if it picks a clock that's not actually running in the hardware.   It's possible to use a TCL script to force the connection to a free running clock, but I'm thinking that it might be more reliable to just instantiate the startup block and use the configuration clock oscillator as a clock source for the debug hub.

 

Maybe I should update this script to do that with recent version of Vivado.

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Observer soma_yow
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Registered: ‎05-01-2017

Re: Vivado TCL script to insert ILA

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I'm using Vivado 2017.4.1. I'm not sure this is a version problem, more of a marginally-knowing-what-I'm-doing problem.

 

I have verified that the constraints get written to 'debug_constraints.xdc', but the implementation phase ignores them.

 

INFO: [Chipscope 16-241] No debug cores found in the current design.

 

I feel I need to somehow merge these constraints with my other design constraints for implementation. Instead they seem to be a separate constraint 'set', where only one set can be active at a time.

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Observer soma_yow
Observer
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Registered: ‎05-01-2017

Re: Vivado TCL script to insert ILA

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Maybe the way that the project flow includes constraints has changed? I've tried N different ways to add the debug_constaints.xdc file to the project w/o success. 

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Observer soma_yow
Observer
2,445 Views
Registered: ‎05-01-2017

Re: Vivado TCL script to insert ILA

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And here's some crazy talk. Why doesn't Xilinx have something exactly like this script as part of the default flow? Add an attribute, boom, it shows up in an ILA. I know there is a GUI thing you can click on to do this, but having to click though this on every fresh build is pure pain.

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1,346 Views
Registered: ‎01-16-2019

Re: Vivado TCL script to insert ILA

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Hi, I tried to use your script as post synthesis tcl.

Problem there is the nessecary constraint files aren't loaded.

What am I doing wrong?

Is it even possible to use that script as post synthesis tcl and if yes, how do I

1. Identify the neccesary xdc files to read

2. The correct order of the xdc files.

(I guess that is done in the "auto-derive constraints" step when you do a open_design)

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Scholar jmcclusk
Scholar
1,326 Views
Registered: ‎02-24-2014

Re: Vivado TCL script to insert ILA

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Did you open the synthesized netlist, and then source the TCL script in the TCL console?   That ought to work.   Also, what version of Vivado are you using?    

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1,262 Views
Registered: ‎01-16-2019

Re: Vivado TCL script to insert ILA

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I am using Vivado 2017.2.1,

I cannot open the synthesized design, (it errors out) both in the post synthesis and the pre implementation (I think I tried pre placement) hook. I think this is due to the fact that we aren't in project mode context when those hooks are executed. I figured out that I have a problem because I let report_clocks be called from the post synthesis hook and it came up empty (like not a single clock was reported). I then started to read all the xdc files (get_files- compile_order constraints -used_in synthesis) first filtered for early then normal then late. First issue was that I have xdc files also included that should be switched off because of genereric exclusion of the IP core.

After I did that, the report_clocks looked betterish. But it's kind of a messy process so I really like input on.:

- is that feasable

- is there a snippet of tcl code of  the 'auto-deriving constraints' step in the open_run command that I could copy.

- How does the rest of HDL Developers deal with auto inserting ILA cores

 

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1,175 Views
Registered: ‎01-16-2019

Re: Vivado TCL script to insert ILA

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So no one has ever done that, or no one likes to share?

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Xilinx Employee
Xilinx Employee
1,166 Views
Registered: ‎10-19-2011

Re: Vivado TCL script to insert ILA

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Hi @rbraunschweiger ,

did you give xapp1295 a look? It is not only useful for transceiver designs. You can add ILAs per design hierarchy.
Or control FF data ports if you like.

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