07-27-2012 09:33 AM - edited 03-18-2014 04:21 PM
|Vivado "How To" Video-based Tutorials
Xilinx is developing QuickTake Video Tutorials in order to assist our users in making the transition from the ISE software tools to the Vivado™ Design Suite. The tutorials are designed to be short clips targeting very specific topics. We’ll continue to add additional videos as well as keep the existing ones current as new software releases roll out.
Learn how to use basic Tcl syntax and language structures to build scripts suitable for use with Xilinx FPGA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls. You will also have the opportunity to use Tcl language constructs with several labs designed to provide you scripting experience within the Vivado® Design Suite.
This course offers detailed training on the Vivado® software tool flow, Xilinx design constraints (XDC), and static timing analysis (STA). Learn to use good FPGA design practices and all FPGA resources to advantage. Learn to fully and appropriately constrain your design by using industry-standard XDC constraints. Learn how the the Vivado IDE design database is structured and learn to traverse the design. Create appropriate timing reports to perform full STA and how to appropriately synthesize your design.
If you have any recommendations or requests for additional Vivado Video Tutorials please send me a private message and we'll ensure to record and post your recommended videos.
08-07-2012 11:01 AM
08-09-2012 10:23 AM
I've been viewing the videos and have notice that when I pause them, then try to resume, they often hang.
I then have to go back to the web page and relaunch the video. Is there some way to avoid this ?
BTW, the reason I paused was to look up a file extension in Appendix A of the Command Line Tools User Guide
Unfortunately, the appendix doesn't include many of the extensions (e.g. .xco, .xci, .xdc, etc.).
When will this appendix be updated ?
01-30-2013 01:07 PM
The command line tool reference guide is specific to ISE. Since ISE will never support the new vivado tools, you will not see this document updated to refer to Vivado. There is an entirely new series of user guides and documentation on Vivado, which is where xdc, xci, etc will be documented.
08-02-2013 03:04 AM
Which documents has detailed information about STA in FPGA ?
I only have Primetime usage experience.
I want to know how to do FPGA STA in my new design.
04-20-2014 11:16 PM
This user guide may help you: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug906-vivado-design-analysis.pdf
04-20-2014 11:25 PM
02-24-2015 02:59 AM
Can anybody tel me how to add zed board in the system generator board description builde for hardware co simulation.]
02-24-2015 10:14 PM
Please start a new thread in correct group to get quality and quick answers to your post.
Check the following discussion: http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/System-Generator-Board-Description-Builder-SBDBuilder-for-Zynq/td-p/395041