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Contributor
Contributor
10,731 Views
Registered: ‎09-20-2013

Vivado target of sub-design is stale

I have two projects that utilizes identical Tcl scripts in non-project mode. When building one I always get the following warning. How do I overcome it?

 

WARNING: [Vivado_Tcl 4-250] The 'Synthesis' target of the sub-design 'my_subdesign' is stale, please manually generate the synthesis target first by executing the command: generate_target {Synthesis} [get_files /home/my_username/prj/my_prj.srcs/sources_1/bd/my_subdesign/my_subdesign.bd]
WARNING: [Vivado_Tcl 4-250] The 'Implementation' target of the sub-design 'my_subdesign' is stale, please manually generate the synthesis target first by executing the command: generate_target {Implementation} [get_files /home/my_username/prj/my_prj.srcs/sources_1/bd/my_subdesign/my_subdesign.bd]

 

Below is a snippet of my Tcl script. I already issues generate_target all which runs synthesis and implementation. Why are the tools suggesting I manually generate the targets a second time? Am I missing something?

 

...

generate_target synthesis [get_ips]
read_bd ${bd}
#reset_target all [get_files ${bd}]
generate_target all [get_files ${bd}]
#report_ip_status -file ip_status.txt
read_verilog ${verilog}
read_xdc ${xdc}

 

synth_design -top ${top}_top -part ${part} -include_dirs ${include_dirs}

...

 

I'm using Vivado 2013.4

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4 Replies
Xilinx Employee
Xilinx Employee
10,723 Views
Registered: ‎09-20-2012

Re: Vivado target of sub-design is stale

Hi,

Can you attach the complete log file?

Thanks,
Deepika.
Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
10,709 Views
Registered: ‎09-20-2012

Re: Vivado target of sub-design is stale

Hi,

 

Thanks for sharing the log.

 

This looks strange. The BD seems to be generated just before synthesis but it still complains.

 

Can you run report_ip_status command after synthesis and show me the log?

 

I doubt if there is a part difference between the block design output products and the part synthesis tool is using.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Xilinx Employee
Xilinx Employee
10,679 Views
Registered: ‎09-20-2012

Re: Vivado target of sub-design is stale

Hi,

The report_ip_status log shows that all IP's in the design are up to date (even the part number matches).

Are you facing any error during synthesis due to this?

This looks like a false warning to me.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Contributor
Contributor
10,672 Views
Registered: ‎09-20-2013

Re: Vivado target of sub-design is stale

The entire project builds fine. I suppose I can simply ignore the warnings.

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