UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
171 Views
Registered: ‎04-19-2018

Write TCL misses Verilog header files

Jump to solution

Vivado 2018.3, project created from the GTH wizard.

When writing the TCL to recreate the project, it misplaces the verilog header file:

gtwizard_ultrascale_0_example_wrapper_functions.v

and adds it as a simulation file, what causes an error when building the recreated project.

Does anyone know how to manually change that on the TCL?

0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
162 Views
Registered: ‎04-19-2018

Re: Write TCL misses Verilog header files

Jump to solution

Adding this seems to do the trick:

set_property file_type {Verilog Header} [get_files gtwizard_ultrascale_0_example_wrapper_functions.v]

It would be better to have real improvements in the tools instead of bundling them and coming with new fancy names. Some of us realize things.

View solution in original post

0 Kudos
3 Replies
Explorer
Explorer
163 Views
Registered: ‎04-19-2018

Re: Write TCL misses Verilog header files

Jump to solution

Adding this seems to do the trick:

set_property file_type {Verilog Header} [get_files gtwizard_ultrascale_0_example_wrapper_functions.v]

It would be better to have real improvements in the tools instead of bundling them and coming with new fancy names. Some of us realize things.

View solution in original post

0 Kudos
Moderator
Moderator
125 Views
Registered: ‎11-04-2010

Re: Write TCL misses Verilog header files

Jump to solution

Hi, @satguy ,

In 2019.2 Vivado, the issue seems to be corrected:

set file "imports/gtwizard_ultrascale_0_example_wrapper_functions.v"

set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]

set_property -name "file_type" -value "Verilog Header" -objects $file_obj

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Explorer
Explorer
123 Views
Registered: ‎04-19-2018

Re: Write TCL misses Verilog header files

Jump to solution

Good to know

0 Kudos