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Explorer
Explorer
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Registered: ‎04-19-2018

Write TCL misses Verilog header files

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Vivado 2018.3, project created from the GTH wizard.

When writing the TCL to recreate the project, it misplaces the verilog header file:

gtwizard_ultrascale_0_example_wrapper_functions.v

and adds it as a simulation file, what causes an error when building the recreated project.

Does anyone know how to manually change that on the TCL?

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Explorer
Explorer
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Registered: ‎04-19-2018

Re: Write TCL misses Verilog header files

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Adding this seems to do the trick:

set_property file_type {Verilog Header} [get_files gtwizard_ultrascale_0_example_wrapper_functions.v]

It would be better to have real improvements in the tools instead of bundling them and coming with new fancy names. Some of us realize things.

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Explorer
Explorer
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Registered: ‎04-19-2018

Re: Write TCL misses Verilog header files

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Adding this seems to do the trick:

set_property file_type {Verilog Header} [get_files gtwizard_ultrascale_0_example_wrapper_functions.v]

It would be better to have real improvements in the tools instead of bundling them and coming with new fancy names. Some of us realize things.

View solution in original post

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Write TCL misses Verilog header files

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Hi, @satguy ,

In 2019.2 Vivado, the issue seems to be corrected:

set file "imports/gtwizard_ultrascale_0_example_wrapper_functions.v"

set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]

set_property -name "file_type" -value "Verilog Header" -objects $file_obj

 

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Highlighted
Explorer
Explorer
222 Views
Registered: ‎04-19-2018

Re: Write TCL misses Verilog header files

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Good to know

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