UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

designutils insert_buffer for skew fixing

Accepted Solution Solved
Observer
Posts: 35
Registered: ‎08-06-2012
Accepted Solution

designutils insert_buffer for skew fixing

I'm not sure where the best place to post this is, but I've noticed the insert_buffer function in the xilinx designutils library is pretty useful for balancing skew in my clock tree.  I don't see any posts about the insert_buffer function though and I'm curious if it is safe to use for this.

 

I have an ASIC design that we really don't want to touch the source on, so HDL inserting anything is undesired.  We have a lot of clocks and auto-BUFG insertion really messes up the skew between clocks.  Using this function allows me to hand tune the clock paths a bit and get closer to meeting hold timing.  So far I've just been inserting a couple BUFGCEs, but I've now noticed I can also insert LUT1s.  I've had limited success with the tools automatically fixing the clock tree issues.

 

Are there problems with this idea that I'm not seeing?  Has anyone done this?


Accepted Solutions
Highlighted
Teacher
Posts: 5,122
Registered: ‎03-31-2012

Re: designutils insert_buffer for skew fixing

@jefedenorsk there is nothing wrong with modifying the netlist after it has been implemented. In fact you add any kind of cell you want, not only buffers or LUT1 but any LUTx and make any other netlist changes you want. The issue is how you make sure that the netlist after you mess with it is still the netlist you undoubtedly verified in RTL. If you're running your verification and timing checks again after you make the changes you propose there is nothing wrong with the flow you suggest.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post


All Replies
Highlighted
Teacher
Posts: 5,122
Registered: ‎03-31-2012

Re: designutils insert_buffer for skew fixing

@jefedenorsk there is nothing wrong with modifying the netlist after it has been implemented. In fact you add any kind of cell you want, not only buffers or LUT1 but any LUTx and make any other netlist changes you want. The issue is how you make sure that the netlist after you mess with it is still the netlist you undoubtedly verified in RTL. If you're running your verification and timing checks again after you make the changes you propose there is nothing wrong with the flow you suggest.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.