export_simulation generates broken paths in vlog.prj

[dario_87]

Hi all,

I have problems with the export_simulation command on Vivado 2017.4 and I can reproduce them on a sample project with only a clock IP.

I'm using this command to export simulation sources and scripts:

export_simulation -of_objects [get_files C:/export_test/tb.v] -export_source_files -directory C:/export_test/exp_sim -ip_user_files_dir C:/export_test/export_test.ip_user_files -ipstatic_source_dir C:/export_test/export_test.ip_user_files/ipstatic -simulator xsim -use_ip_compiled_libs -force -quiet

but the paths that I get in the vlog.prj file are wrong:

verilog xil_defaultlib --include "srcs/incl" \
srcs/srcs/ip/clk_wiz_0/xil_defaultlib/clk_wiz_0_clk_wiz.v \
"srcs/ip/clk_wiz_0/clk_wiz_0.v" \
"srcs/top.v" \
"srcs/tb.v" \

verilog xil_defaultlib "glbl.v"

nosort

errors:

• there is duplicated srcs/ on the first path
• on the second path the library name is missing (in this case I have only 1 IP but this happens to all of them)

Of course the compiler fails.

The correct content should be:

verilog xil_defaultlib --include "srcs/incl" \
srcs/ip/clk_wiz_0/xil_defaultlib/clk_wiz_0_clk_wiz.v \
"srcs/ip/clk_wiz_0/xil_defaultlib/clk_wiz_0.v" \
"srcs/top.v" \
"srcs/tb.v" \

verilog xil_defaultlib "glbl.v"

nosort

Am I missing something or is this a bug in the tool?

Regards,

Dario

[ansarimo]

Hello @dario_87 ,

Make sure your IP is not locked if it is locked then upgrade it using Report IP status and check if it helps.

Also, I would recommend you to export simulation using the GUI flow and check if still you are getting the same issue.

for exporting simulation using Vivado: open Vivado--> open project-->File --> Export --> Export simulation.

Compare this newly generated .prj file with the older one and check if this newly generated file contains the paths as you expected.

Regards,

Ansari Hunen

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[dario_87]

Hi @ansarimo ,

the IP is not locked. I tried exporting from GUI but I get the same result.

I attached a zip to re-create the project so you can verify yourself.

The steps to reproduce are:

source create_prj.tcl
expand design sources -> right click on the IP -> generate output products
File --> Export --> Export simulation, then select 'Vivado simulator' and tick 'copy source files to export directory'

Ticking 'absolute path' still generates wrong paths with different types of errors.

Dario

[ansarimo]

Hi @dario_87 ,

I was able to reproduce the issue at my end, it looks like export_simulation is adding an extra "srcs" before the IP path.

As a workaround, try removing that extra "srcs" from the IP path and check if still, you are getting the same issue, this issue is not reproducible on Vivado 2020.1 as you can see in the below snapshot.

Please try it on the latest Vivado i.e. 2020.1 and let me know if still you are facing the same issue.

Regards,

Ansari Hunen

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[dario_87]

Hi @ansarimo ,

thank you for trying my script.

Do you get also the second error? (missing xil_defaultlib in the path)

I know that if I edit the file it works, the problem is that I'm developing a scripted flow for simulation so is not acceptable that users have to manually edit the file. Also this is a sample, in the real project I have hundreds of paths and the errors that show up might be different (I need to verify).

And I have to use version 2017.4 for this project (only other version I have is 2019.2 where the problem still exists).

I can think of 2 workarounds:

- create a script to fix the .prj (but this can be more or less difficult based on the error patterns in the paths. If it was only the double srcs it would have been easy)

- fix the export_simulation source file (on windows C:\Xilinx\Vivado\2017.4\data\XilinxTclStore\tclapp\xilinx\projutils\export_simulation.tcl). I don't know if this is possible though, sure I'm not able to do it. I wonder if someone in Xilinx could have a look and produce a patch

Still I'm surprised that no one else had this problem.

How do people run simulation with xsim in batch mode if you cannot generate the vlog.prj?

Dario

[ansarimo]

Hi @dario_87 ,

I suspect this is a design specific issue as we haven't seen such an issue in the past.

Another thing which I observed is while exporting simulation if you don't select "copy source files to export directory" than the .prj file has paths as expected as you can see in the below snapshot.

Also, try to export simulation with the Xilinx example design and check if still, you are facing the same issue, I tried at my end but didn't notice such behavior.

Hope this helps.

Thanks and Regards,

Ansari Hunen

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[dario_87]

Hi @ansarimo ,

I get the same error on lots of project that I tried and also on Xilinx example 'Base Microblaze' so I don't think it can be design specific.

Which example design did you use?

Yes, without export sources it works, I can use that but it would have been useful to copy the source file for my use case.

Dario