08-03-2017 03:34 AM
Above picture is schematics of 'minimum Value Generator(mVG)'
When input V1 and V2 come into mVG, comparator(Comp) compares what is the minimum value between them.
After that Comp outputs 'cp' signal which is 0 or 1. Depend on cp value, minimum value(mV) is determined using MUX.
I wonder how to make a comparator using logic gates.
I mean, how many AND/XOR/OR/NOT gates are inside a comparator and how they connected each other.
Please, somebody help me.
08-03-2017 04:10 AM
In an FPGA everything is implemented as lookup tables anyway, so the logic gates are largely irrelevant. Anything up to two 3-bit inputs can be done in a single 6-input lookup table.
For a discrete logic design, it depends on how many bits you have. The most simple comparator (1-bit) that outputs Y = 1 when A > B would be:
Y = A & ~B
One NOT gate and one AND gate.
For a larger comparator, the most efficient method is probably a subtractor with the output being the sign bit.
08-03-2017 05:43 AM
In almost all cases, the answer is "write the code, synthesize it, and let the tools tell you".
The code in question is trivial - in Verilog it would be
assign cp = (v1 < v2);
assign mV = cp ? v1 : v2;
And, as @u4223374 said, the result will be in LUTs and CARRY chain elements, not gates.
08-04-2017 05:41 AM
There are a number of ways to build an mVG from scratch, for example:
Let's take a look at the first two just to get an idea about the gates required:
A one bit comparator circuit typically requires 2 inverter, 2 AND gates and one NOR gate so a total of 5 gates.
For a single bit solution, we are only interested in one output of the comparator (e.g. A>B) or 2 gates, but to be able to combine it into larger blocks, we need at least two outputs or 4 gates.
The logic to combine two single bit blocks into a two bit solution requires two gates (1 OR, 1 AND).
So we have a total of N*4+(N-1)*2-2 gates for an N bit comparator with a single output.
A full adder circuit typically consists of 2 XOR, 2 AND and one OR gate.
To make it a full subtractor only requires to invert one input which adds an inverter.
The carry/borrow of the last stage will be the selector for the MUX.
We do not use the result, so 1 gate can be eliminated per stage and we don't have a carry input in the first stage.
This gives a total of N*4-2 gates for an N bit subtractor with a single carry/borrow output.
The multiplexer in our case is simple and basically consists of 2 AND gates and an inverter for the selection.
This results in a total of N*2+1 gates for an N bit wide 2:1 multiplexer.
So summing up we roughly need N*6 gates to implement an N bit wide mVG.
Note that as @u4223374 and @avrumw already explained, modern FPGAs do not use gates but instead they use lookup tables (LUTs) which can replace any [N-input, M-output] logic circuit within the limits of those lookup tables ([6,2] for recent Xilinx FPGAs).
So Q <= B when B > A else A; for example will result in roughly 2*N LUTs plus a bunch of carry blocks.
Hope that clarifies,