UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Scholar embedded
Scholar
2,895 Views
Registered: ‎06-09-2011

questions regarding phys_opt-design

Hi all,

 

I am developing code for a board based on xc7a15t-3fgg484. I am reading two 7-bit DDR data port with their 500 MHz clock. As it is at the speed boundaries of Artix-7 series I am using a FIFO to write such fast data and read it at half speed with two times bus width!. 

My design completely works for a 128 word FIFO depth and timing fails on some internal IP core signals if I increase the depth of FIFO to 256 words. When I look at the timing report I see two or three signals failed in WNS - WNS > -1nS - which is an indication of setup time violation. 

I came across to tcl command phys_opt_design and read up on it in Top 5 Timing Closure Techniques. There, I realized if I use this command with various directives it may improve my timing. I have attached timing report of what it could do and it turns out that I don't have timing errors any longer. Here are some questions regarding next steps I have to do:

  1. I am wondering if I can rely on this report or not?
  2. I am also going to make bit file updated.  would these recently generated files be used for generating bit stream files or not?
  3. Why project status & summery in GUI is not updated according to this recently placed & routed design?!
  4. I Still see the red items of timing report has not disappeared!. Should I reopen it or not?

 

I would appreciate any help

Hossein

 

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
2,887 Views
Registered: ‎09-20-2012

Re: questions regarding phys_opt-design

Hi @embedded

 

If you are using project mode (GUI flow), go to Implementation settings and enable the "phys_opt_design", select desired directive and save the settings. Later rerun implementation.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Scholar embedded
Scholar
2,851 Views
Registered: ‎06-09-2011

Re: questions regarding phys_opt-design

Hi,

I have added some directives like : -fanout_opt, -plcement_opt, routing_opt, -rewire in the menu as you see in below picture:

 

Phys_opt.jpg

However, it didn't meet timing constraint and again it failed!.

Although I have changed my design a little, I am wondering if there's a way I can find out which optimization best fits my WNS problem.

 

Thanks,

Hossein

0 Kudos
Xilinx Employee
Xilinx Employee
2,848 Views
Registered: ‎09-20-2012

Re: questions regarding phys_opt-design

Hi @embedded

 

Try using "Performance_*" Implementation strategies. 

 

You need to look at the timing report to understand why the path is failing.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Scholar embedded
Scholar
2,843 Views
Registered: ‎06-09-2011

Re: questions regarding phys_opt-design

Hi @vemulad,

 

The reason for failure - after using another clock in the design - is setup time violation:

 

Summary				
Name	Path 1			
Slack	-0.003ns			
Source	sAdcData_reg[14]/C   (rising edge-triggered cell FDRE clocked by oAdcDco_AdcClk  {rise@0.000ns fall@1.000ns period=2.000ns})			
Destination	MyFifo_INST/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC_sp.ram/DIBDI[16]   (rising edge-triggered cell RAMB36E1 clocked by oAdcDco_AdcClk  {rise@0.000ns fall@1.000ns period=2.000ns})			
Path Group	oAdcDco_AdcClk			
Path Type	Setup (Max at Slow Process Corner)			
Requirement	2.000ns (oAdcDco_AdcClk rise@2.000ns - oAdcDco_AdcClk rise@0.000ns)			
Data Path Delay	1.182ns (logic 0.313ns (26.491%)  route 0.869ns (73.509%))			
Logic Levels	0  			
Clock Path Skew	-0.082ns			
Clock Uncertainty	0.048ns			

Now, my questions increased!. Why should that part of design be affected by another part of design when it doesn't share common clock path or signals?!

How I can fix this issue?

 

Thanks,

Hossein

 

 

0 Kudos
Scholar embedded
Scholar
2,842 Views
Registered: ‎06-09-2011

Re: questions regarding phys_opt-design

Hi @vemulad,

 

I can't figure out why I should be receiving such error between a clock and itself?!

clock2clock.jpg

Thanks,

Hossein

 

0 Kudos