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daxman
Newbie
Newbie
23,125 Views
Registered: ‎07-03-2013

set_property SEVERITY {Warning} [get_drc_checks NSTD-1] not working

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Whenever I try to use set_property SEVERITY {Warning} [get_drc_checks NSTD-1] when generating the bit file, I get ther error:  "ERROR: [Common 17-165] Too many positional options when parsing 'NSTD-1', please type 'write_bitstream -help' for usage info."  I need to use this set_property because I am not giving constraints for all 63 of the nets.  I am just going with what was inferred during implimentation.  Thanks a ton for the help!

 

 

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vemulad
Xilinx Employee
Xilinx Employee
34,399 Views
Registered: ‎09-20-2012

Hi,

 

I just re-checked this at my end. The previous constraint will not be getting reflected in the XDC.

 

Open implemented design and type the below command in tcl console save design and re-run processes.

 

set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
 

Thanks,

Deepika.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
23,122 Views
Registered: ‎09-20-2012

Hi,

 

The syntax of the command is correct.

 

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

 

Where are you including this constraint?

 

Thanks,

Deepika.

Thanks,
Deepika.
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amit.g
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23,093 Views
Registered: ‎07-03-2013

Hello All,

 

I am getting following Error while bit stream generation:

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 36 out of 36 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: axi_c2c_s2m_intr_out[3:0], axi_c2c_selio_rx_data_in[12:0], axi_c2c_selio_tx_data_out[12:0], axi_c2c_link_error_out, axi_c2c_link_status_out, axi_c2c_multi_bit_error_out, axi_c2c_selio_rx_clk_in, axi_c2c_selio_tx_clk_out, reset_rtl.


[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 36 out of 36 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: axi_c2c_s2m_intr_out[3:0], axi_c2c_selio_rx_data_in[12:0], axi_c2c_selio_tx_data_out[12:0], axi_c2c_link_error_out, axi_c2c_link_status_out, axi_c2c_multi_bit_error_out, axi_c2c_selio_rx_clk_in, axi_c2c_selio_tx_clk_out, reset_rtl.

 

What should i do?

 

where should i include following command:

set_property SEVERITY {Warning} [get_drc_checks UCIO-1

 

PLease help me .

 

Thanks,

AMit Garg

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vemulad
Xilinx Employee
Xilinx Employee
23,090 Views
Registered: ‎09-20-2012

Hi,

 

You can write in to TCL console of vivado and save design .Re-run the processes.

 

It is recommended that you specify LOC/IO standards for all top level ports in the design. But if you want to overcome the errors without doing this you can covert the error message in to warning using the above tcl command.

 

Thanks,

Deepika.

Thanks,
Deepika.
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amit.g
Visitor
Visitor
23,085 Views
Registered: ‎07-03-2013

Thanks Deepika.. i have run with your suggestion by writing the commands into tcl_console and save the design. After that i ran the whole proces(SYNTHESIS,IMPLEMENTTION and BITSTREAM GENERATION) but issue is occuring again.

 

any idea on what i have done wrong?

 

Please let knoe if you need any file or information.

 

Thanks,

Amit Garg

 

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vemulad
Xilinx Employee
Xilinx Employee
23,081 Views
Registered: ‎09-20-2012

Hi,

 

Did you write both these below commands? Did the tool return any warning message when they are written?

 

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

 

After saving the design check the XDC file to see if these constraints are saved.

 

Thanks,

Deepika.

Thanks,
Deepika.
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amit.g
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23,075 Views
Registered: ‎07-03-2013

i wrote both of commands and no warning reported.

 

But strange thing is that it is not added in any XDC file.

 

Regards,

Amit

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vemulad
Xilinx Employee
Xilinx Employee
34,400 Views
Registered: ‎09-20-2012

Hi,

 

I just re-checked this at my end. The previous constraint will not be getting reflected in the XDC.

 

Open implemented design and type the below command in tcl console save design and re-run processes.

 

set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
 

Thanks,

Deepika.

Thanks,
Deepika.
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amit.g
Visitor
Visitor
23,066 Views
Registered: ‎07-03-2013

Re-run menas only bitstream generation or whole synthesis, implementation and bitsteream?

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vemulad
Xilinx Employee
Xilinx Employee
23,063 Views
Registered: ‎09-20-2012

After writing this constraint in to tcl console save the design. Now Synthesis and Implementation processes will be marked out of date. You need to re-run synthesis and implementation processes.

 

Thanks,

Deepika.

Thanks,
Deepika.
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amit.g
Visitor
Visitor
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Registered: ‎07-03-2013

Problem Solved!!!!!!

 

Thanks a lot Deepika for your quick responses :)

 

If i need to add all the top level constraint which are not added automatically, in which files should i add or in which directory should i add so that that will not be overwritten?

 

Regards,

Amit Garg

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vemulad
Xilinx Employee
Xilinx Employee
15,126 Views
Registered: ‎09-20-2012

Hi Amit,

 

Good to hear that it worked.

 

Can you please elaborate the new query?

 

Thanks,

Deepika.

Thanks,
Deepika.
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amit.g
Visitor
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15,117 Views
Registered: ‎07-03-2013

Hello Deepika,

 

Actually There are some Ports at the top level which were not defined automatically by Vivado tool to any Location (even iostandard was not defined) due to which i was facing the above issue during bitfile generation. Now i need to add those ports in ucf file(or xdc file) but i see there are lots of XDC fils are present in a database.

 

So i need to know which files i should update so that the constraint written by me would not be updated with any other constraint files.

 

Thanks,

Amit Garg

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vemulad
Xilinx Employee
Xilinx Employee
15,115 Views
Registered: ‎09-20-2012

Hi Amit,

 

The vivado tool does assign pin locations and default IO standard to all the top level ports in the design.

 

The error message is given by the tool  to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.

 

In Vivado GUI, in the sources window, you can check the active constraint set  marked as "(active)" under "constraints". You can add the constraints to any of the XDC in the active constraint set.

 

Thanks,

Deepika.

Thanks,
Deepika.
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