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jreinauld
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Registered: ‎02-24-2017

set_property synth_checkpoint_mode None does not work

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Hello all,

I am currently trying to switch from Vivado project flow to Vivado non-project flow (currently using 2019.1).

I have built a toy project for the exercise, with one block design file and a TCL build script (see attached).

I get the following error:
ERROR: [BD 41-1942] The design 'mb_subsystem.bd' is set for Out-of-Context synthesis mode Hierarchical (Out of context per IP) but is not fully generated. Please ensure that design sources are fully generated before adding them to non-project flow. You can also try setting the mode to None (Global Synthesis), or use Save Project As to save your work in a project flow to use this mode.

To solve this issue, I followed UG994: Designing IP Subsystems Using IP Integrator > Chapter 10: Using IP Integrator in Non-ProjectMode > Creating a Flow in Non-Project Mode and I added the following command:

set_property synth_checkpoint_mode None [get_files <path to the bd file>]

However, it does not solve the issue.

For my toy project, a workaround is to modify the BD, replacing "synth_flow_mode": "Hierarchical" with "synth_flow_mode": "None", but after that I will not be the owner of the BD files so I need to make it work properly.

Can anyone tell me where my mistake is please?

I attached all the files needed to reproduce the issue

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ashishd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hi @jreinauld ,

This is discrepancy with UG994 and I've filed CR to get it fixed. Basically if read_bd command itself fails, then adding some commands after this to rectify the problem cannot work, as flow will break at this command only.

So in order to fix this problem, you can do it in either of the ways -

1. In original project, make sure that if you set synth_checkpoint_mode of block design to Hierarchical or Singular, then you must generate output products.

2. If you don't want to generate output products, then in original project you should set synth_checkpoint_mode to None and then read that bd in non-project mode using read_bd command.

Regards,
Ashish
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jreinauld
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Registered: ‎02-24-2017

Can anyone help?
Unless I am mistaken I am following UG994 by the book and yet it does not work : (

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Try putting the "generate_target" command right after  "set_property synth_checkpoint_mode None [get_files <path to the bd file>]".

-vivian

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jreinauld
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Registered: ‎02-24-2017

Hi @viviany 

Thanks for your answer.

I have tried that and it does not work.

Here is my updated script:

 

set source_directory ./src

set output_directory ./output
file mkdir ${output_directory}

create_project -verbose -in_memory
set_property PART xc7k325tffg900-2 [current_project]
set_property BOARD_PART xilinx.com:kc705:part0:1.6 [current_project]
set_property target_language VHDL [current_project]

read_bd -verbose ${source_directory}/mb_subsystem.bd
make_wrapper -verbose -files [get_files ${source_directory}/mb_subsystem.bd] -top
read_vhdl -verbose -library work ${source_directory}/hdl/mb_subsystem_wrapper.vhd
set_property synth_checkpoint_mode None [get_files ${source_directory}/mb_subsystem.bd]
generate_target -verbose all [get_files ${source_directory}/mb_subsystem.bd]

set_property top mb_subsystem_wrapper [current_fileset]

synth_design -verbose
opt_design -verbose
place_design -verbose
phys_opt_design -verbose
route_design -verbose

write_bitstream -verbose ${output_directory}/mb_subsystem_wrapper.bit

write_mem_info -verbose "${output_directory}/mb_subsystem_wrapper.mmi"
exec updatemem --meminfo "${output_directory}/mb_subsystem_wrapper.mmi" --data "${source_directory}/hello_world.elf" --bit "${output_directory}/mb_subsystem_wrapper.bit" --proc mb_subsystem_i/microblaze_0 --out "${output_directory}/updated_mb_subsystem_wrapper.bit"

 

 

and here is the log:

 

$ vivado -mode batch -source build.tcl 

****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source build.tcl
# set source_directory ./src
# set output_directory ./output
# file mkdir ${output_directory}
# create_project -verbose -in_memory
# set_property PART xc7k325tffg900-2 [current_project]
# set_property BOARD_PART xilinx.com:kc705:part0:1.6 [current_project]
# set_property target_language VHDL [current_project]
# read_bd -verbose ${source_directory}/mb_subsystem.bd
ERROR: [BD 41-1942] The design 'mb_subsystem.bd' is set for Out-of-Context synthesis mode Hierarchical (Out of context per IP) but is not fully generated. Please ensure that design sources are fully generated before adding them to non-project flow. You can also try setting the mode to None (Global Synthesis), or use Save Project As to save your work in a project flow to use this mode.
ERROR: [Common 17-39] 'read_bd' failed due to earlier errors.

    while executing
"read_bd -verbose ${source_directory}/mb_subsystem.bd"
    (file "build.tcl" line 12)
INFO: [Common 17-206] Exiting Vivado at Wed Feb 24 12:07:36 2021...

 



It is actually the read_bd command that fails, rather than the generate_target command.

Any idea about that?

Thanks,

- Julien

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viviany
Xilinx Employee
Xilinx Employee
918 Views
Registered: ‎05-14-2008

Go back to the project that you created the .bd and generate output products for the .bd in that project.

Make sure all products are fully generated.

Does this help?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
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ashishd
Xilinx Employee
Xilinx Employee
904 Views
Registered: ‎02-14-2014

Hi @jreinauld ,

The mistake here is, you are missing the important Note mentioned on page 194 of UG994. Here is link for the same -

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug994-vivado-ip-subsystems.pdf#page=194

So the requirement is, before using read_bd command, the block design must be fully generated using either of the ooc mode. 

If you don't want this, then for original block design, synth_checkpoint_mode should be set to None (which means Global mode of output product generation).

 

Regards,
Ashish
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jreinauld
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Registered: ‎02-24-2017

Hi @viviany , @viviany.

Thanks for your help.

There is something I still don't understand.

 


If it is mandatory that either:
- the BD has been fully generated
OR
- the BD "synth_flow_mode" is set to "None"

Then what is the purpose of the command set_property synth_checkpoint_mode None?

 

 

@ashishd in the UG994, I read:

Note: If the block design is not generated then you will need to generate the output products for theblock design by adding the following commands:
read_bd <path to the bd file>
set_property synth_checkpoint_mode None [get_files <path to the bd file>]
generate_target all [get_files <path to the bd file>]

If I understand correctly, this is supposed to solve my case (BD with "synth_flow_mode" is set to "Hierarchical", not generated yet, used in non-project flow)

 

What am I missing here?

 

Thanks,

- Julien

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ashishd
Xilinx Employee
Xilinx Employee
818 Views
Registered: ‎02-14-2014

Hi @jreinauld ,

This is discrepancy with UG994 and I've filed CR to get it fixed. Basically if read_bd command itself fails, then adding some commands after this to rectify the problem cannot work, as flow will break at this command only.

So in order to fix this problem, you can do it in either of the ways -

1. In original project, make sure that if you set synth_checkpoint_mode of block design to Hierarchical or Singular, then you must generate output products.

2. If you don't want to generate output products, then in original project you should set synth_checkpoint_mode to None and then read that bd in non-project mode using read_bd command.

Regards,
Ashish
----------------------------------------------------------------------------------------------
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jreinauld
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Registered: ‎02-24-2017

Hi @ashishd,

Thanks a lot for coming back to me.

So as I understand it, in non-project flow, when working with a BD file, it is mandatory that either the BD is already generated OR the BD has "synth_flow_mode": "None".
And the command set_property synth_checkpoint_mode None [get_files /path/to/the/bd/file] cannot be used to workaround this requirement.

I have one final question: in which other case or context the command set_property synth_checkpoint_mode None [get_files /path/to/the/bd/file] is actually useful?

Many thanks for not giving up on this question!

- Julien

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ashishd
Xilinx Employee
Xilinx Employee
790 Views
Registered: ‎02-14-2014

Hi @jreinauld ,

Yes your understanding is correct.

To answer your question, if you set synth_checkpoint_mode of block design to value 'None', it means that output products of block design will be generated in Global mode. This is useful if you wish to disable out of context mode for output product generation for block design and generate output products which can be used in top down synthesis flow of whole design. You can find more information about all three modes of output product generation and their significance here -

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug994-vivado-ip-subsystems.pdf#page=100

Regards,
Ashish
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jreinauld
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Registered: ‎02-24-2017

Allright,

So I finally understood \o/

Given a BD in my project (either a 'real' project in project flow or an in-memory project in non-project flow), the set_property synth_checkpoint_mode command must be used just before the generate_target command in order to choose between Global Synthesis, OOC per IP or OOC per BD.

Everything is clear now, thanks a lot!

- Julien

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