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Participant gmoore
Participant
1,137 Views
Registered: ‎08-29-2016

'set _property verilog_define' Not working in synthesis

Hi,

I am synthesising a design that originally included a verilog file with some `defines, that was included as a global define.

 

I would prefer to replace this file with individual `set_property verilog_define DEFINE_NO1 [get_filesets sources_1]` commands in my tcl script, but these defines are not being picked up in the synthesis. 

 

The script looks like this : 

# Start script

create_project -force prj_name ./proj_name_dir/ -part xcvu9p-flga2104-2l-e
set_property design_mode RTL [current_fileset]

 

add_files {file list here}

 

set_property verilog_define DEFINE_01 [get_filesets sources_1]
set_property verilog_define DEFINE_02 [get_filesets sources_1]

 

launch_runs -runs synth_1 -dir ./
wait_on_run synth_1

# End script

 

Is my usage of the set_property verilog_define correct in this script ? 

 

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4 Replies
Moderator
Moderator
1,100 Views
Registered: ‎11-04-2010

Re: 'set _property verilog_define' Not working in synthesis

Hi, @gmoore ,
You can refer to the below example command:
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define DEFINE_01=1} -objects [get_runs synth_1]

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Participant gmoore
Participant
1,090 Views
Registered: ‎08-29-2016

Re: 'set _property verilog_define' Not working in synthesis

Hi hongh,

 

I have tried the options you suggested, and it did not work - the script looks like this : 

 

# Start Script

create_project -force prj_name ./prj_name_dir -part xcvu9p-flga2104-2l-e
set_property design_mode RTL [current_fileset]

add_files $FILES_LIST
set_property top prj_top [get_property srcset [current_run]]

#set_property verilog_define DEFINE_01 [get_filesets sources_1]
#set_property verilog_define DEFINE_02 [get_filesets sources_1]
#set_property verilog_define DEFINE_03=9 [get_filesets sources_1]

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define DEFINE_01} -objects [get_runs synth_1]
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define DEFINE_02} -objects [get_runs synth_1]
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define DEFINE_03=9} -objects [get_runs synth_1]

launch_runs -runs synth_1 -dir ./
wait_on_run synth_1
# End script

 

When I include a .h file with the same `define values, and set it as a global include file, the `defines within that .h file are present in the synthesis, but not when I use the method you suggested. 

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Scholar markcurry
Scholar
1,060 Views
Registered: ‎09-16-2009

Re: 'set _property verilog_define' Not working in synthesis

 

In non-project scripting mode, the following works fine for us:

 

synth_design -verbose -top {foo}  -verilog_define "FPGA_VARIANT_01=1" 

This correctly overrides any previous defines already in the source file.

 

Don't know if you're able to migrate to non-project scripting mode or not...

 

Regards,

 

Mark

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Moderator
Moderator
997 Views
Registered: ‎11-04-2010

Re: 'set _property verilog_define' Not working in synthesis

Hi, @gmoore ,
Which version of Vivado are you using?
Could you try your run in 2018.1?
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Don't forget to reply, kudo, and accept as solution.
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