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Observer zhengweibin
Observer
9,710 Views
Registered: ‎11-05-2014

shared BRAM between ZYNQ PS and PL

mems.png

 

 

 

I have a peripheral P to be tested. P has 2 BRAM blocks. I connect the bram blocks to PS through axi.

 

The implementation has the warning messages below.

launch_runs impl_1
[BD 41-237] Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_0/BRAM_PORTA(OTHER) and /axi_bram_ctrl_0/BRAM_PORTA(BRAM_CTRL)
[BD 41-237] Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_1/BRAM_PORTA(OTHER) and /axi_bram_ctrl_1/BRAM_PORTA(BRAM_CTRL)
[BD 41-237] Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_0/BRAM_PORTA(OTHER) and /axi_bram_ctrl_0/BRAM_PORTA(BRAM_CTRL)
[BD 41-237] Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_1/BRAM_PORTA(OTHER) and /axi_bram_ctrl_1/BRAM_PORTA(BRAM_CTRL)

Implementation
[Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.

 

When I tried to set in TCL console as noted in http://forums.xilinx.com/t5/New-Users-Forum/Shared-BRAM-Zynq-PS-PL/m-p/506269#M12413, the command failed.

set_property CONFIG.MASTER_TYPE {BRAM_CTRL} [get_bd_intf_ports BRAM_PORTA]
[Common 17-55] 'set_property' expects at least one object.

 

So what can I do?

 

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3 Replies
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Observer zhengweibin
Observer
9,672 Views
Registered: ‎11-05-2014

Re: shared BRAM between ZYNQ PS and PL

Another try:

 

set_property CONFIG.MASTER_TYPE {BRAM_CTRL} [get_bd_intf_pins /blk_mem_gen_0/BRAM_PORTB]

CRITICAL WARNING: [BD 41-737] Cannot set the parameter MASTER_TYPE on /blk_mem_gen_0/BRAM_PORTB. It is read-only.

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Observer zhengweibin
Observer
9,670 Views
Registered: ‎11-05-2014

Re: shared BRAM between ZYNQ PS and PL

I am using Vivado 2014.4.
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8,506 Views
Registered: ‎09-16-2015

Re: shared BRAM between ZYNQ PS and PL

Hi, I am also getting the following critical warning after validation for the connection between AXI BRAM Controller and Block Memory Generator for one of my design for Virtex-7 2000TFLG1925-2:

CRITICAL WARNING: [BD 41-237] Bus Interface property MASTER_TYPE does not match between /blk_mem_gen_1/BRAM_PORTA(OTHER) and /axi_bram_ctrl_0/BRAM_PORTA(BRAM_CTRL)

 

In order to solve this,

I tried executing the following command from TCL console of Vivado 2015.2 to resolve this critical warning, but, it's not helping. Please find below the error message :

set_property CONFIG.MASTER_TYPE {axi_bram_ctrl_0/BRAM_PORTA} [get_bd_intf_ports blk_mem_gen_1/BRAM_PORTA]
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports blk_mem_gen_1/BRAM_PORTA'
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

 

Can anybody help to resolve this ? Thanks.

 

Rakesh

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