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jas_kchew
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Registered: ‎07-21-2009

tcl file did not produce the same bus width result as the original BD

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Hi,

I am facing an issue with the generation of the BD using TCL.I have a working BD which has a 16 bits FIFO data bus connecting to the DMA s_axis_s2mm_tdata. I exported this BD to a TCL file using write_bd_tcl command. However when I re-generate this tcl file on a new project, the data interface at the dma becomes 32 bits. When I try to Generate Block Design, vivado gave me a width mismatch warning. The Stream Data Width in the AXI-DMA is "Auto". I can't change the width to 16bits from the GUI. I am connection each signal in the S_AXIS_S2MM independently as I need to control the tlast and tvalid signals.

How can I resolve the issue such that the new BD is able to recognize the 16bits but instead of 32 bits and auto propagate it down to the DMA? In the first design I had to do some trial and error in order to get the DMA to recognize the 16bits bus as well, such as creating/deleting the DMA and reinstate etc. 

 

regards

Jason

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jas_kchew
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Registered: ‎07-21-2009

I have got the problem solved with the help of Krishna from Xilinx. Apparently it is the independent signal connection that is causing the problem. The solution is to connect the AXI-Buses as a whole  (i.e. S_AXIS_S2MM to M_AXIS). Then separately connect the individual signals that are required to be pulled out to the external ports.

 

Thanks!

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balkris
Xilinx Employee
Xilinx Employee
4,729 Views
Registered: ‎08-01-2008
check this related posts
https://forums.xilinx.com/t5/Vivado-TCL-Community/upgrade-bd-tcl-script-created-with-write-bd-tcl-from-older-to/td-p/680994
http://xillybus.com/tutorials/vivado-version-control-packaging
https://www.xilinx.com/support/answers/56421.html
Thanks and Regards
Balkrishan
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jas_kchew
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Registered: ‎07-21-2009

Hi,

 

I am using the same tool version (2015.2.1) in both instances. What I found is that since the AXI DMA-"Stream Data Width(Auto)" parameter is auto, no setting is specified in the tcl file. I supposed Vivado should auto recognize the Data Width size and auto generate the right parameter. However it doesn't.

 

regards

Jason

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yashp
Moderator
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Registered: ‎01-16-2013
Hi,

Can you please check with latest version of Vivado after migration?
Vivado 2016.3

Thanks,
Yash
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jas_kchew
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Registered: ‎07-21-2009

Hi,

 

Unfortunately, I have to stay with this vivado version of 2015.2.1 as I am working with an on-going project and a team of engineers. It will be difficult for me to change a version at the moment. Any suggestion of a work around for such parameter propagation problem other than trial & error and hope that the tool somehow pick up the changes done?

 

Thanks.

 

regards

Jason

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pratham
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Registered: ‎06-05-2013

@jas_kchew Is it possible to provide us a test case so we can take a look at it and provide some workaround? 

-Pratham

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jas_kchew
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Registered: ‎07-21-2009

I have got the problem solved with the help of Krishna from Xilinx. Apparently it is the independent signal connection that is causing the problem. The solution is to connect the AXI-Buses as a whole  (i.e. S_AXIS_S2MM to M_AXIS). Then separately connect the individual signals that are required to be pulled out to the external ports.

 

Thanks!

View solution in original post

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