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ViennaAudio
Adventurer
Adventurer
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Registered: ‎07-01-2020

trim and stretch function implementation

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Hi.

 

I have to implement the function explained in attached picture, please help!!!

 

Kind regards

trimstretch.jpg
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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@ViennaAudio,

Why create new arrays?  Why not just step though this array twice as fast, or three times as fast, etc, when reading from it?

I must still be missing something here.

Dan

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@ViennaAudio,

I'm not sure I understand the problem statement from just this information well enough to comment upon it here.

Dan

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watari
Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ViennaAudio 

 

Using PLL as a sampling clock and FIFO or some memory controller to trim signal seem best solution.

Would you consider them ?

 

BTW, how to implement them ? By tcl ?

If so, it is not able to implement it by tcl.

 

Best regards,

ViennaAudio
Adventurer
Adventurer
663 Views
Registered: ‎07-01-2020

 

hope i can explain it clearly

 

given an array of 1024 16bits values, (it could be whatever waveform or even noise)

fill a new array of 1024 16bits values containing 2 cycles of original array,

fill a new array of 1024 16bits values containing 3 cycles of original array

fill a new array of 1024 16bits values containing 4 cycles of original array,

up to 10 cycles, so 10 arrays

thx for your attention

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ViennaAudio
Adventurer
Adventurer
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Registered: ‎07-01-2020

thx a lot for your attention,

i surely posted this in a wrong board... so ye, no tlc to implement this.

Could you explain me better your idea pls?

 

Best regards

 

 

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dgisselq
Scholar
Scholar
653 Views
Registered: ‎05-21-2015

@ViennaAudio,

Why create new arrays?  Why not just step though this array twice as fast, or three times as fast, etc, when reading from it?

I must still be missing something here.

Dan

View solution in original post

watari
Teacher
Teacher
641 Views
Registered: ‎06-16-2013

Hi @ViennaAudio 

 

If you use FPGA, I suggest you to use Vivado to build FPGA design.

Also, you can find MMCM as PLL and some FIFO and memory controller in it.

 

Best regards,

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ViennaAudio
Adventurer
Adventurer
640 Views
Registered: ‎07-01-2020

Thx Dan

 

I know, that is a really good point, and i would do that if this operation was the last one of the design.

there are two more operations to do after this one

This block is an harmonic generator for unknown incoming waveform

i'm quite scared of implementing 9 wt oscillators, could that lead to sync problems?

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