cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
2,330 Views
Registered: ‎09-05-2017

unknow error -----Incompatible complex type aasignment

Daer @anunesgu @woodsd @hongh and the rest of professionals 

 

I have a unknown error. I see that some others have the same Problem in this forum, I could not solve the Problem yet.

 

The error is unknow for me and it about Incompatible complex type assignment.

 

Could you please tell me how can I fix the error?

 

BR;

Pixi

 

 
FPAG1.png
0 Kudos
6 Replies
Highlighted
Moderator
Moderator
2,300 Views
Registered: ‎02-09-2017

Hi @pixel2017,

 

I verified internally and there is a common issue with that IP when the project is targeted to VHDL language.

 

The AXI VIP can only act as a protocol checker when contained within a VHDL hierarchy. To use the virtual part of the AXI verification component, it must be in a Verilog hierarchy.

 

Could you try changing the project and simulation target language to Verilog, click reset output products, click Generate outputs products and then click simulation.

 

You can find more info about that IP, including simulation example, in the following document: AXI Verification IP v1.1 - PG267

 

Thanks.

 

Andre Guerrero

Product Applications Engineer

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Highlighted
Observer
Observer
2,282 Views
Registered: ‎09-05-2017

Hi @anunesgu

 

Thank you for your response. I will try that as soon as possible.

about the example of testbench of VIP AXI, I used and mixed two examples of Xilinx. I am not sure, I must use my own IP block in the testbench(Threshold), I mean just AXI VIP is enough to be used in testbech? my testbech was so far a way from solution?

Is there any Xilinx example that shows how to run master and slave IPs like mine and any Block (not VIP) in the middle?

 

Thanks & Best Regards,

Pixi

 

0 Kudos
Highlighted
Observer
Observer
2,248 Views
Registered: ‎09-05-2017

Dear @anunesgu @amaccre

 

I changed the target langauge to Verilog, but still the error excists.:(

 

as you can see in below, I changed the target language to in Setting place. is that what you meant? I also reset and ...,

nothing happend.

 

BR;Fatemeh

 

 

 

 

 

FPGA2.png
0 Kudos
Highlighted
Observer
Observer
2,210 Views
Registered: ‎09-05-2017

Dear Experts and Xilinx emplyees and professionals, 

 

I could not solve the Problem yet . Could you please navigate me. my Code is Attachement. 

 

Thank you so much

BR;

Pixi

 

 

0 Kudos
Highlighted
Contributor
Contributor
1,107 Views
Registered: ‎05-19-2018

Hi @pixel2017, I have been able to resolve the exact same issue in Vivado 2017.2 by setting the target language to Verilog and then creating a Verilog wrapper around the bd.

Regards, Christiaan

** kudo if the answer was helpful **
** accept as solution if your question is answered **
0 Kudos
Highlighted
Explorer
Explorer
768 Views
Registered: ‎10-12-2018

My simulator works weel in Mixed mode.

I had the same error after I clean my project. (So if thi is the case there is a file that I shouldn't deleted). The problematic file is the xml file beside the IP descriptor xci. Keep/store it in your version control.

The solution is the same (for me) 

  1. Regenerate the Verification-IP from scratch (delete the xci too, and add a new IP)
  2. There is an *.xml beside the *.xci IP descriptor. Store the xml too. The root of the problem was that my version controlled the xml, which is needed for the VIP, if you using legacy versions of Vivado.

I use:

  • Win10
  • Vivado 2017.4
0 Kudos