10-16-2017 09:48 AM
Daer @anunesgu @woodsd @hongh and the rest of professionals
I have a unknown error. I see that some others have the same Problem in this forum, I could not solve the Problem yet.
The error is unknow for me and it about Incompatible complex type assignment.
Could you please tell me how can I fix the error?
10-16-2017 01:09 PM - edited 10-16-2017 01:15 PM
I verified internally and there is a common issue with that IP when the project is targeted to VHDL language.
The AXI VIP can only act as a protocol checker when contained within a VHDL hierarchy. To use the virtual part of the AXI verification component, it must be in a Verilog hierarchy.
Could you try changing the project and simulation target language to Verilog, click reset output products, click Generate outputs products and then click simulation.
You can find more info about that IP, including simulation example, in the following document: AXI Verification IP v1.1 - PG267
10-16-2017 02:29 PM
Thank you for your response. I will try that as soon as possible.
about the example of testbench of VIP AXI, I used and mixed two examples of Xilinx. I am not sure, I must use my own IP block in the testbench(Threshold), I mean just AXI VIP is enough to be used in testbech? my testbech was so far a way from solution?
Is there any Xilinx example that shows how to run master and slave IPs like mine and any Block (not VIP) in the middle?
Thanks & Best Regards,
10-17-2017 02:46 AM
10-18-2017 04:26 AM
11-16-2018 03:34 AM - edited 11-16-2018 03:35 AM
Hi @pixel2017, I have been able to resolve the exact same issue in Vivado 2017.2 by setting the target language to Verilog and then creating a Verilog wrapper around the bd.
03-21-2019 02:46 AM
My simulator works weel in Mixed mode.
I had the same error after I clean my project. (So if thi is the case there is a file that I shouldn't deleted). The problematic file is the xml file beside the IP descriptor xci. Keep/store it in your version control.
The solution is the same (for me)