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amir.massah
Adventurer
Adventurer
824 Views
Registered: ‎10-12-2018

write_project_tcl - wrong filesets

Hi to all,

I am trying to manage my Vivado projects with write_project_tcl in Vivado 2016.4.

I am getting errors when I am running the TCL generated by write_project_tcl. In my projects, I have a lot of my own IPs in which I have used block memories and I have problems with the instantiated Xilinx IP inside my IPs. I looked inside the TCL, I can see that it looks for a filesets named as the IP which I have customized and instantiated inside my own IPs. This is an example:

# Set IP repository paths
set obj [get_filesets SHCRef_Mem144x144x1536]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../KA91_FPGA/KA91_TCLTest/cores"]" $obj

I guess I should change something in my project before generating the TCL by write_project_tcl.

Thank you very much.

Regards,

Amir

 

 

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3 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
806 Views
Registered: ‎05-22-2018

Hi @amir.massah ,

Try using write_bd_tcl instead of write_project_tcl. Please check page no.1536 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug835-vivado-tcl-commands.pdf

Thanks,

Raj

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amir.massah
Adventurer
Adventurer
800 Views
Registered: ‎10-12-2018

Hi @rshekhaw,

Thank you for your reply.

But I have also other IPs in addition to the block design in my project that I want to manage them. The write_bd_tcl does not create a project and add files and so on.

 

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asbuscemi
Visitor
Visitor
471 Views
Registered: ‎08-01-2019

I am also having an issue with the ip_repo_paths.  I'm using Vivado 2019.1 and when I use the write_project_tcl, the resulting tcl file does not point to the correct place relative to the origin directory.  It's always one folder too high in the hierarchy.  Whenever I generate the script I have to go to that line in the tcl script and add a "../" after the origin directory.  Seems like a bug that should be fixed.  

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