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Visitor
Visitor
8,256 次查看
注册日期: ‎11-28-2015

关于使用vivado2015.4进行行为仿真的问题

本人使用vivado2015.4对UG937的行为仿真实例进行实践操作,发现行为仿真无法实现,系统显示:

  • [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/ZYNQ_Example/project_xsim/project_xsim.sim/sim_1/behav/elaborate.log' file for more information.

在TCL栏中是这样显示的:

Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Assembler messages:
Error: can't open xsim.dir/testbench_behav/obj/xsim_0.win64.as for reading: No such file or directory
Assembler messages:
Error: can't open xsim.dir/testbench_behav/obj/xsim_1.win64.as for reading: No such file or directory
ERROR: [XSIM 43-3410] Failed to compile one of the generated C files.
Please recompile with "-mt off -v 1" switch to identify which design unit failed.
INFO: [USF-XSim-99] Step results log file:'E:/ZYNQ_Example/project_xsim/project_xsim.sim/sim_1/behav/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'E:/ZYNQ_Example/project_xsim/project_xsim.sim/sim_1/behav/elaborate.log' file for more information.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:24 . Memory (MB): peak = 1137.246 ; gain = 0.000

 

我全程都是严格按照UG937的步骤进行操作的,而且也检查了没发现哪有错误,到底是什么问题?

本人用的是64位windows系统,综合啥的都没有问题,唯独只有仿真无法使用,这是不是vivado的BUG呢?求帮助~谢谢!

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Visitor
Visitor
7,434 次查看
注册日期: ‎11-28-2015

怎么没人回啊?都一个月了,给个解释~

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Visitor
Visitor
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注册日期: ‎02-27-2012

E:/ZYNQ_Example/project_xsim/project_xsim.sim/sim_1/behav/elaborate.log' file for more information
建议看看elaborate.log里面可能有更详细的log

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Visitor
Visitor
285 次查看
注册日期: ‎12-18-2019

你好,请问您的问题解决了吗?我现在也遇到了类似这样elaborate step failed的问题,elaborate.log详细如下:

Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: D:/vivado/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 230519e5147c4cb6a471a343b4da4104 --debug typical --relax --mt 2 -d FPGA= -L axi_bram_ctrl_v4_1_1 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TB_behav xil_defaultlib.TB xil_defaultlib.glbl -log elaborate.log -cc gcc -sv_lib dpi
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 30 for port 'io_axi4_0_ar_bits_addr' [H:/lowrisc/src/test/verilog/nasti_ram_sim.sv:59]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 30 for port 'io_axi4_0_aw_bits_addr' [H:/lowrisc/src/test/verilog/nasti_ram_sim.sv:72]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 64 for port 'dina' [H:/lowrisc/src/main/verilog/fstore2.v:69]
Completed static elaboration
Starting simulation data flow analysis

 

这就是elaborate.log中全部的的信息,实在是没找到哪里有问题。

期待您的回复!

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Xilinx Employee
Xilinx Employee
274 次查看
注册日期: ‎02-28-2019

@jiutianzhige 

请开新帖,并附上相关log文件和背景说明。

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Scholar
Scholar
213 次查看
注册日期: ‎05-29-2018

典型仿真的位宽不匹配问题
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Visitor
Visitor
183 次查看
注册日期: ‎12-18-2019

我照着这几个warning改了一下不匹配位宽的几个线性端口,但是还是不能仿真成功。以下是console出来的信息:

INFO: [VRFC 10-2263] Analyzing SystemVerilog file "H:/lowrisc/fpga/board/nexys4_ddr/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sim_1/new/TB.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module TB
INFO: [VRFC 10-2263] Analyzing Verilog file "H:/lowrisc/fpga/board/nexys4_ddr/lowrisc-chip-imp/lowrisc-chip-imp.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
"xvhdl --relax -prj TB_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "H:/lowrisc/fpga/board/nexys4_ddr/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_bram_ctrl_dummy/sim/axi_bram_ctrl_dummy.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'axi_bram_ctrl_dummy'
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 2178.148 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '14' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/lowrisc/fpga/board/nexys4_ddr/lowrisc-chip-imp/lowrisc-chip-imp.sim/sim_1/behav/xsim'
"xelab -wto 230519e5147c4cb6a471a343b4da4104 --debug typical --relax --mt 2 -d "FPGA=" -L axi_bram_ctrl_v4_1_1 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TB_behav xil_defaultlib.TB xil_defaultlib.glbl -log elaborate.log -cc clang -sv_lib dpi"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: D:/vivado/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 230519e5147c4cb6a471a343b4da4104 --debug typical --relax --mt 2 -d FPGA= -L axi_bram_ctrl_v4_1_1 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TB_behav xil_defaultlib.TB xil_defaultlib.glbl -log elaborate.log -cc clang -sv_lib dpi
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis

 

这就是console最后的一段信息,前面的都是分析模块的信息。一直都是在console中执行到Starting simulation data flow analysis之后跳出来错误,错误如下:

[USF-XSim-62] 'elaborate' step failed with error(s) while executing 'H:/lowrisc/fpga/board/nexys4_ddr/lowrisc-chip-imp/lowrisc-chip-imp.sim/sim_1/behav/xsim/elaborate.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

 

然后我就去查看elaborate.log,里边的内容如下:

Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: D:/vivado/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 230519e5147c4cb6a471a343b4da4104 --debug typical --relax --mt 2 -d FPGA= -L axi_bram_ctrl_v4_1_1 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TB_behav xil_defaultlib.TB xil_defaultlib.glbl -log elaborate.log -cc clang -sv_lib dpi
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis

 

也是到Starting simulation data flow analysis这一步就什么也不显示了。

然后我发现在simulation的setting中有个elaborate的设置,设置如下:

xsim.elaborate.xelab.more_options*后面设置的是-cc clang -sv_lib dpi。原来我设置的是-cc gcc -sv_lib dpi但是这两个都不行。

 

我的开发环境是windows 10,vivado 2019.1.

因为这个工程原来是由我在Ubuntu 16.04中的vivado 2019.1生成的,现在拷贝到windows里来用了,不知道是不是版本的问题。但是我在ubuntu中运行仿真也会出现elaborate step failed这样的错误。

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