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xlgforever
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导入ISE的工程,并升级IP核后,行为仿真时xil_defaultlib报错

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我在Vivado中导入了一个ISE的工程,其中包含一个CORDIC IP核以及其他的加法器乘法器等IP核,导入后提示我升级IP,CORDIC IP核升级之后,其接口与ISE中的版本发生了变化,因此根据端口的变化我修改了对应的Verilog文件。然后运行了行为仿真,提示报错如下:

INFO: [VRFC 10-3107] analyzing entity 'tb_sol_sincos'
ERROR: [VRFC 10-2987] 'sol_sincos' is not compiled in library 'xil_defaultlib' [D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd:209]
ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd:77]
INFO: [VRFC 10-3070] VHDL file 'D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd' ignored due to errors

我使用的IP核都是 IP Catalog中自带的,导入的加法器和乘法器都不存在这个问题。

请问要怎么解决

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xlgforever
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在调整了如下图所示的设置之后,从工程中删除IP及其文件,重新生成新的相同的IP,仿真可以正确进行了,但是不知道是为什么:

微信截图_20200715144057.png

虽然我取消勾选了上述选项,但是查看生成的IP核的文件似乎没有任何变化,仍然有demo_tb文件夹,不过仿真可以正确运行。

顺便问一下,ISE中的自动生成tb文件的功能Vivado有什么办法实现吗?需要测试的模块很多,而且端口复杂,写tb文件很费时。

在原帖中查看解决方案

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xlgforever
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更新:尝试删除该IP(从工程中移除并删除磁盘上对应的文件),并在vivado中重新生成一个一模一样的IP,还是相同的错误

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hongh
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仿真时是带着XCI文件直接做仿真,还是调用IP的源文件做仿真?

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xlgforever
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我做的仿真只是所有模块中的一个小模块,该模块并不包含对CORDIC IP核的使用,但是由于CORCID IP核也在仿真资源中,所以进行任何仿真时应该都会像上面的tcl控制台输出的内容那样对所有的仿真资源进行检查,检查到CORDIC  IP这里时就失败:

INFO: [VRFC 10-3107] analyzing entity 'sub20_20sub20_ga'
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sub25_25sub25_ga/sim/sub25_25sub25_ga.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'sub25_25sub25_ga'
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_sol_sincos'
ERROR: [VRFC 10-2987] 'sol_sincos' is not compiled in library 'xil_defaultlib' [D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd:209]
ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd:77]
INFO: [VRFC 10-3070] VHDL file 'D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.srcs/sources_1/ip/sol_sincos/demo_tb/tb_sol_sincos.vhd' ignored due to errors
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:19 . Memory (MB): peak = 2134.020 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '19' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Vivado_WorkSpace/spoke_021_vivado/spoke_021_vivado.sim/sim_1/behav/xsim/xvhdl.log'

这个tb_sol_sincos.vhd应该是IP模块自动生成的,存在于下图的demo_tb中:

微信截图_20200715110508.png

但是其他导入并升级后的加法器或乘法器IP核目录中并没有这个文件夹。能直接删掉吗?

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xlgforever
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似乎不能删除该demo_tb文件夹,删掉后会报错找不到里面的文件

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viviany
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report_compile_order -used_in simulation [get_ips <ip_name>]

用这个命令看一下这个ip的compile order,错误里提到的这个模块是否编译到了xil_defaultlib里

命令行的语法未必正确,如果有不对的地方,用report_compile_order -help查一下

-vivian

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graces
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建议查看一下simulation sources的顶层是否为你所希望的tb。理论上来说,仿真的对象不包含这个IP的话,不应该将IP source包含进编译列表。

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xlgforever
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report_compile_order -used_in simulation [get_ips sol_sincos]
ERROR: [Common 17-165] Too many positional options when parsing 'sol_sincos', please type 'report_compile_order -help' for usage info.
report_compile_order -help
report_compile_order

Description: 
Report the compile order by analyzing files and constructing a hierarchy.

Syntax: 
report_compile_order  [-fileset <arg>] [-missing_instances] [-constraints]
                      [-sources] [-used_in <arg>] [-file <arg>] [-append]
                      [-of_objects <args>] [-quiet] [-verbose]

Usage: 
  Name                  Description
  ---------------------------------
  [-fileset]            FileSet to parse to determine compile order
  [-missing_instances]  Report missing instances in the design hierarchy
  [-constraints]        Report the constraint compile order
  [-sources]            Report the source compile order
  [-used_in]            Specify the used in filter.
  [-file]               Filename to output results to.
  [-append]             Append output to existing file
  [-of_objects]         Get 'file' objects of these types: 'file fileset ip 
                        reconfig_module'.
  [-quiet]              Ignore command errors
  [-verbose]            Suspend message limits during command execution

Categories: 
Project

Description:

  Report the compilation order of files in the various active filesets:
  constraints, design sources, and simulation sources.

  This command returns the order of file processing for synthesis,
  implementation, and simulation. The report can be limited by specifying the
  fileset of interest with -fileset, or using the -constraints option or
  -sources option.

  The -used_in option lets you report the processing order of files used in
  Synthesis, Simulation, or one of the implementation steps, according to the
  value of the USED_IN property.

  By default the report is returned to the Tcl console, or standard output,
  but it can also be written to a file.

Arguments:

  -of_objects <args> - (Optional) Report the files that are associated with
  the specified filesets, sub-designs, or reconfiguration modules. The
  default is to search all filesets. When -compile_order and -used_in are
  specified, the -of_objects switch will only accept a single fileset, or a
  single sub-design such as an IP core, Block Design, or DSP design. A
  sub-design is also known as a composite file.

  Note: The -of_objects option requires objects to be specified using the
  get_* commands, such as get_cells or get_pins, rather than specifying
  objects by name. In addition, -of_objects cannot be used with a search
  <pattern>.

  -fileset <arg> - (Optional) Limit the report to the specified fileset.

  -missing_instances - (Optional) Return the list of cells that are missing
  source files in the current or specified fileset.

  -constraints - (Optional) Report the compilation order of the constraint
  files in the current design, including constraints for any IP in the
  design.

  -sources - (Optional) Report the compilation order of files found in the
  sources_1 fileset of design sources.

  -used_in <arg> - (Optional) Accepts one of the enumerated values of the
  USED_IN property for files, and returns files matching the specified value.
  Valid values for this option include the following: synthesis, simulation,
  or implementation. Refer to the Vivado Design Suite Properties Reference
  Guide (UG912) for information on the USED_IN property and its supported
  values.

  -file <arg> - (Optional) Write the report into the specified file. The
  specified file will be overwritten if one already exists, unless -append is
  also specified.

  Note: If the path is not specified as part of the file name, the file will
  be written into the current working directory, or the directory from which
  the tool was launched.

  -append - (Optional) Append the output of the command to the specified file
  rather than overwriting it.

  Note: The -append option can only be used with the -file option.

  -quiet - (Optional) Execute the command quietly, returning no messages from
  the command. The command also returns TCL_OK regardless of any errors
  encountered during execution.

  Note: Any errors encountered on the command-line, while launching the
  command, will be returned. Only errors occurring inside the command will be
  trapped.

  -verbose - (Optional) Temporarily override any message limits and return
  all messages from this command.

  Note: Message limits can be defined with the set_msg_config command.

Examples:

  The following example reports the compilation order of the active filesets
  in the current design:

    report_compile_order 
    

  The following returns a list of cells with missing source files in the
  current design, and appends the report to the specified file:

    report_compile_order -missing_instances -file C:/Data/report1.txt -append 
    

  The following command lists the compile order of the files in the active
  constraint set:

    report_compile_order -constraints 
    

See Also:

   *  current_fileset
   *  get_files
   *  update_compile_order

命令语法没有错,但是无法执行

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xlgforever
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仿真的底层的确为所希望测试的模块作为顶层,如图:

微信截图_20200715140954.png

其他的是从ISE工程中导入的仿真文件,这些导入的仿真文件中有些包含了报错的IP。

现在想要单独测试每一个小模块,所以基本上需要从最底层的模块向上测试,所以会不停的写一些新的仿真文件,并在Simulation Settings里轮流将其设置为顶层并进行行为仿真。

所以现在是执行任何一个小的模块的仿真,都会检查所有包含在仿真资源中的IP核,检查到该cordicIP核时,显示失败

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xlgforever
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注册日期: ‎05-23-2019

在调整了如下图所示的设置之后,从工程中删除IP及其文件,重新生成新的相同的IP,仿真可以正确进行了,但是不知道是为什么:

微信截图_20200715144057.png

虽然我取消勾选了上述选项,但是查看生成的IP核的文件似乎没有任何变化,仍然有demo_tb文件夹,不过仿真可以正确运行。

顺便问一下,ISE中的自动生成tb文件的功能Vivado有什么办法实现吗?需要测试的模块很多,而且端口复杂,写tb文件很费时。

在原帖中查看解决方案

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viviany
Xilinx Employee
Xilinx Employee
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注册日期: ‎05-15-2008

这个选项和结果看不出有什么关联。

可能原工程的某个错误在这些操作后被修正了

很遗憾Vivado没有自动生成testbench模板的功能

-vivian

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如果您认为帖子有帮助,请点击“奖励”。谢谢!
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graces
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注册日期: ‎07-17-2008

如vivian所说,这个选项不应该影响到编译列表,估计是移植过程中哪块损坏出问题了。

vivado的IP可右键选择,如有IP Example Design,可以选择打开,有完整的IP例程验证。

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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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