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Newbie yulolo
Newbie
243 次查看
注册日期: ‎01-08-2019

部分信号综合后变成了generated clock ,应该怎么解决?

使用的是vivado2018,仿真结果没有问题,但是综合后尝试添加时钟时,一些计数器被综合成了生成时钟,会影响实现的结果吗?如何才能解决?时钟.png

 

 

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Moderator
Moderator
212 次查看
注册日期: ‎11-05-2010

回复: 部分信号综合后变成了generated clock ,应该怎么解决?

Hi, @yulolo ,

方便提供您的opt.dcp吗?

您先看下报出的cell 的原理图, 确认 寄存器Q端是否驱动了时钟信号.

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