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Visitor raindropxhu
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142 次查看
注册日期: ‎11-07-2018

2018.2 使用systemverilog和C仿真时报错,使用-cc clang无效

使用如下官方方法无效

The XSim compiler executable xelab can be instructed to use clang compiler in one of the following three ways:

 

  1. In Vivado IDE, open the Simulation Settings dialog box, and specify "-cc clang" in the xsim.elaborate.xelab.more_options field. 
  2. For Vivado Tcl (in interactive or batch mode), run the following command before the running launch_simulation command. Substitute sim_1 with the correct simulation set name if your simulation set name is different or if you have multiple simulation sets. 
    set_property -name {xsim.elaborate.xelab.more_options} -value {-cc clang} -objects [get_filesets sim_1]
  3. If xelab is run directly by the user, add "-cc clang" to the xelab command line.

(一)TCL输出信息:

Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.glbl
Waiting for 1 sub-compilation(s) to finish...
xsim.dir/top_behav/obj/xsim_2.win64.obj:xsim_2.c:(.text+0xf4): undefined reference to `c_display'
collect2.exe: error: ld returned 1 exit status
ERROR: [XSIM 43-3238] Failed to link the design.

(二)elaborate.log信息:

Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: G:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 9cffe27136f84cd7a3c2ad48516702ae --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log -cc clang
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.glbl
Waiting for 1 sub-compilation(s) to finish...
ERROR: [XSIM 43-3238] Failed to link the design.

 

 

 

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Xilinx Employee
Xilinx Employee
55 次查看
注册日期: ‎07-17-2008

回复: 2018.2 使用systemverilog和C仿真时报错,使用-cc clang无效

2018.3试过吗?

示例工程可以提供的话,我们在本地可做复现,如果是工具问题,可以提交研发做修正。

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