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Adventurer
Adventurer
547 次查看
注册日期: ‎10-18-2019

[Board 49-69] Validation failed for board file

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[Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml:
Frequency Parameter not provided for audio_clock

1.1 systhesis后报出两个warning,第一个waring就是[Board 49-69] Validation failed for board file (第二个warning是[Constraints 18-5210] No constraints selected for write.)

vivado_ME3ym3LPMA.png

1.2 所有操作都参考了这篇文章:vavado使用 

1.3 选用的开发板及开发板文件(在新建工程时选择的)是arty-a7(35T )(对于FPGA为Artix7-35T )

1.4 vavado2019.1

---------------------------------------

疑问:

2.1 为什么回报这个错误?

2.2 

Inkedvivado_ME3ym3LPMA_LI.jpgwarning中显示的目录为何是pynq(我操作中直接按照 vivado使用链接中的方法来的)?

pynq开发板和arty-a7开发板所对应文件肯定不同!

 

2.3 怀疑是这里的设置,

vivado_IWdcsGsDeF.pngsetting里的default project dictionary之前可能被改到pynq里了

 

 

 

 

 

 

2.4 但是,改了目录之后重新综合Synthesis,这两个warning仍然存在.

chrome_gLf800g6Eu.png

-----------------------------------------------------------------------------------

我应该如何才能解决这样的问题呢?

 

标记 (1)
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1 解答

已接受的解答
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Adventurer
Adventurer
418 次查看
注册日期: ‎10-18-2019

 谢谢您和您同事的回复

在之前的Synthesis中warnings仍然存在的情况下,进一步将原有工程implementation和Generate bitstream。所有警告如下:

vivado commands: (1 warning)

  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock

 

synthesis:(2 warnings)

  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock
  • [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

implemetation (2 warnings)

  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock
  • [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock
  • [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information.
  •  
  • --------------------------------------------------------------------------------------
  • Validation failed for board file  警告可能是后续警告的原因

在原帖中查看解决方案

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Moderator
Moderator
544 次查看
注册日期: ‎07-01-2019

你好 @drsdrb ,

 

这个界面的Project Device是你的板卡吗?

第二个warning可以忽略

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vivado.jpg
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Xilinx Employee
Xilinx Employee
532 次查看
注册日期: ‎02-28-2019

Hi @drsdrb ,

在tcl里面输入:

get_parts -of_object [current_project]

查看一下返回结果。

其次Viviado有些产生的警告是起提醒作用,如果报的是critical warning或error可能需要修正。

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Don't forget to reply, kudo, and accept as solution.
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Adventurer
Adventurer
436 次查看
注册日期: ‎10-18-2019

您好,我已确认,所在工程General处为我的板卡 Arty A7-35。

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Adventurer
Adventurer
432 次查看
注册日期: ‎10-18-2019
您好,在tcl里面输入:

get_parts -of_object [current_project]后返回
xc7a35ticsg324-1L
-------------------------------
另外,在Setting的General下的project device里显示板卡文件为 Arty A7-35(xc7a35ticsg324-1L)
两者一致
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Highlighted
Adventurer
Adventurer
419 次查看
注册日期: ‎10-18-2019

 谢谢您和您同事的回复

在之前的Synthesis中warnings仍然存在的情况下,进一步将原有工程implementation和Generate bitstream。所有警告如下:

vivado commands: (1 warning)

  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock

 

synthesis:(2 warnings)

  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock
  • [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

implemetation (2 warnings)

  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock
  • [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
  • [Board 49-69] Validation failed for board file D:/Xilinx/Vivado/2019.1/data/boards/board_files/PYNQ-Z2_board_file_v1.0/PYNQ-Z2 board file v1.0/A.0/board.xml: Frequency Parameter not provided for audio_clock
  • [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information.
  •  
  • --------------------------------------------------------------------------------------
  • Validation failed for board file  警告可能是后续警告的原因

在原帖中查看解决方案

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Highlighted
Visitor
Visitor
245 次查看
注册日期: ‎07-01-2020
你这个[Board 49-69]的警告最后怎么解决的呢
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Xilinx Employee
Xilinx Employee
235 次查看
注册日期: ‎05-15-2008

This is a rather old post.

Please create a new post for your question.

Thanks

Vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Adventurer
Adventurer
164 次查看
注册日期: ‎10-18-2019
是的,Arty35T对应的
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