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Visitor xuyangfirst
Visitor
334 次查看
注册日期: ‎08-27-2018

Independent clock block RAM FIFO simulation wr_data_count 复位值始终非0

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器件:  XCKU040-ffva1156-2-e

FIFO: native 模式  32x2048, fall through, more accurate data count,

除reset 和clock之外,输入均为低

 

问题现象:

每次复位之后若干clock, wr_data_count 值会变成2。rd_data_count 值正确(0). 

写入若干数据后,wr_data_count 值会恢复成正常。

再次复位后, wr_data_count 值又会成为错误的值(2)

 

 

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Xilinx Employee
Xilinx Employee
331 次查看
注册日期: ‎02-28-2019

回复: Independent clock block RAM FIFO simulation wr_data_count 复位值始终非0

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Hi @xuyangfirst ,

wr_data_count提供的值不是精确的,具体可以参考:https://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v13_2/pg057-fifo-generator.pdf page 111

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Xilinx Employee
Xilinx Employee
332 次查看
注册日期: ‎02-28-2019

回复: Independent clock block RAM FIFO simulation wr_data_count 复位值始终非0

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Hi @xuyangfirst ,

wr_data_count提供的值不是精确的,具体可以参考:https://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v13_2/pg057-fifo-generator.pdf page 111

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Don't forget to reply, kudo, and accept as solution.
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Visitor xuyangfirst
Visitor
314 次查看
注册日期: ‎08-27-2018

回复: Independent clock block RAM FIFO simulation wr_data_count 复位值始终非0

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Thanks YangC

看到 write/read data count 的相应介绍了。看来用这两个信号做触发需要特别注意

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