Loss of timing constraints

[geyi1990]

The output clock of PLL can be seen in timming summary at the end of synthesis, and there will be no clock at the end of implementation. Why is the timing constraint lost?

[hongh]

Do you mean all the constraints are removed or only the output clock of PLL are removed?

Generally please confirm that you only apply create_clock on the input of PLL, and the output clock of PLL will be derived.

[graces]

@geyi1990 你说的no clock是指open implemented design后，运行report_clocks看不到PLL的输出时钟对象，还是说timing summary里面看不到这些输出时钟cover的路径？请具体予以说明。

综合后分析都在的话，至少在综合阶段时钟约束是OK的。也可以检查一下impl阶段有无关于时钟约束的critical warning。

[geyi1990]

timing summary里面看不到这些时钟。比如我PLL产生了3个时钟 clk1 clk2 clk3,综合后report timing summary就可以看到这些时钟。实现之后再report timing summary就只有一个clk2了。

[geyi1990]

only the output clock of PLL are removed

[hongh]

打开综合/实现设计后，report_clock 的结果分别是什么？

方便提供综合后的DCP吗？

[geyi1990]

刚追查原因发现在综合的时候约束已经异常，原因是因为我在DFF输出产生的衍生时钟无效（DFF丢失），为什么DFF也会被优化掉吗？

[hongh]

一般来说寄存器不太会被优化掉，除非没有得到输入信号或者输出信号的没有被应用到. 这寄存器和PLL是什么关系？

[viviany]

Does the DFF output Q pin drive anything? If it is a clock, does it drive any sequential elements?

Any loadless logics will be removed in Synthesis. And if the drivers becomes loadless after the logics they drive are removed, the drivers will be removed too.

So check if the fanout of the DFF finally drives the FPGA output pins.

-vivian