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Observer willyeyeball
Observer
694 次查看
注册日期: ‎12-21-2018

Vivado HLS Version 2017.4 可否做 OpenCL 之 C simulation (Pre-synthesis validation) ?

Hi 您好 :

我使用 HLS(2017.4) 去驗證 OpenCL (*.cl 檔) : Run C simulation

不過一直出現以下 Error :

ERROR: [SIM 211-100] CSim file generation failed with errors. prj_vadd_test:solution1 2019/1/18 下午 04:21:50

我編譯器已經選擇 Clang 了 , 不過遇到 *.cl 檔, 就過不去,

請問應該如何解決呢?

Best Regards

willyeyeball

2019-01-18 16-22-25 的螢幕擷圖.png2019-01-18 16-23-13 的螢幕擷圖.png

 

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Moderator
Moderator
633 次查看
注册日期: ‎05-23-2018

回复: Vivado HLS Version 2017.4 可否做 OpenCL 之 C simulation (Pre-synthesis validation) ?

Hi, @willyeyeball

有没有详细的报错信息呢?

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Xilinx Employee
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回复: Vivado HLS Version 2017.4 可否做 OpenCL 之 C simulation (Pre-synthesis validation) ?

UG902, 第310页,OpenCL API C Test Benches描述了验证OpenCL API C kernel需要的特殊处理。请对照看看是否符合要求。

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf

另外,HLS的Example Design的Coding Example部分也有opencl_kernel例子供参考。

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Xilinx Employee
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注册日期: ‎05-15-2008

回复: Vivado HLS Version 2017.4 可否做 OpenCL 之 C simulation (Pre-synthesis validation) ?

Console窗口里看看log里有没有其他error

-vivian

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Observer willyeyeball
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注册日期: ‎12-21-2018

回复: Vivado HLS Version 2017.4 可否做 OpenCL 之 C simulation (Pre-synthesis validation) ?

Hi 您好 :

1. 

UG902, 第310页,OpenCL API C Test Benches描述了验证OpenCL API C kernel需要的特殊处理。请对照看看是否符合要求。

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf

==> 我想我的程式碼應該有符合, 但編譯是不會過的(只要有*.cl 檔的存在), 以下為我的程式碼 :

 vadd.testbench.c :

#include <stdio.h>
#include <stdlib.h>
#include "vadd.h"

// Testbench code
int main(int argc,char** argv)
{
#if 0
unsigned int n=VADD_WORKGROUP_SIZE_X;
vadd_type *h_a;
vadd_type *h_b;
vadd_type *h_c;
vadd_type *h_r;

size_t bytes=n*sizeof(vadd_type);
h_a=(vadd_type*) malloc(bytes);
h_b=(vadd_type*) malloc(bytes);
h_c=(vadd_type*) malloc(bytes);
h_r=(vadd_type*) malloc(bytes);

srand(11888);

int i;
for(i=0;i<n;i++)
{
h_a[i]=vadd_type_rand;
h_b[i]=vadd_type_rand;
h_c[i]=0;
}

for(i=0;i<n;i++)
{
h_r[i]=h_a[i]+h_b[i];
}

hls_run_kernel("vadd_kernel",h_a,256,h_b,256,h_c,256,n,1);

int errors=0;
for(i=0;i<n;i++)
{
if(h_c[i]!=h_r[i])
{
errors++;
}
}

return (errors>0)?1:0;
#endif
}

 

vadd.cl (沒有內容):

#if 0
#include <clc.h>
#include "vadd.h"


__attribute__ ((reqd_work_group_size(VADD_WORKGROUP_SIZE_X,VADD_WORKGROUP_SIZE_Y,VADD_WORKGROUP_SIZE_Z)))

__kernel void vadd_kernel(
__global vadd_cl_type *a,
__global vadd_cl_type *b,
__global vadd_cl_type *c,
uint n
)
{
/*
__attribute__((xcl_pipeline_workitems))
{
const int id=get_global_id(0);
if(id>=n) return;

c[id]=a[id]+b[id];
}
*/
}

#endif

 

==> 編譯顯示的錯誤訊息是 (如下所示) :

Starting C simulation ...
/opt/Xilinx_HLS_2017/Vivado/2017.4/bin/vivado_hls /home/roger/willy/work/Vivado_HLS_2017/Prj_OpenCL_vadd/prj_vadd_test/solution1/csim.tcl
INFO: [HLS 200-10] Running '/opt/Xilinx_HLS_2017/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'root' on host 'roger-All-Series' (Linux_x86_64 version 4.7.0.intel.r5.0) on Mon Jan 21 17:18:23 CST 2019
INFO: [HLS 200-10] On os Ubuntu 16.04.5 LTS
INFO: [HLS 200-10] In directory '/home/roger/willy/work/Vivado_HLS_2017/Prj_OpenCL_vadd'
INFO: [HLS 200-10] Opening project '/home/roger/willy/work/Vivado_HLS_2017/Prj_OpenCL_vadd/prj_vadd_test'.
INFO: [HLS 200-10] Opening solution '/home/roger/willy/work/Vivado_HLS_2017/Prj_OpenCL_vadd/prj_vadd_test/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xczu9eg-ffvb1156-2-i'
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
WARNING: [HLS 200-40] clang: error: cannot specify -o when generating multiple output files
ERROR: [SIM 211-100] CSim failed with errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source /home/roger/willy/work/Vivado_HLS_2017/Prj_OpenCL_vadd/prj_vadd_test/solution1/csim.tcl"
invoked from within
"hls::main /home/roger/willy/work/Vivado_HLS_2017/Prj_OpenCL_vadd/prj_vadd_test/solution1/csim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C simulation.

==> 這跟 testbench 沒關係, 是我只要加入 vadd.cl 就會編譯錯誤(即使完全沒有內容), Project 拿掉 vadd.cl (當然testbench的內容也拿掉), 編譯就會成功, 我的問題是 HLS 是否支援 OpenCL? 如果支援OpenCL, 為何加入 *.cl

就會編譯錯誤?

Best Regards

willyeyeball 

 

 

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