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Visitor
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709 次查看
注册日期: ‎07-01-2020

Vivado2019.2在Generate Output Product时经常卡死

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Vivado版本是2019.2 创建Vivado工程并创建Block Designer,添加ZYNQ7 CPU IP并配置PS的MIO与DDR后,执行Run Block Automation 并保存system.bd,右击 system.bd, 单击Generate Output Products。基本每次都会导致Vivado程序卡死。请问这个怎么解决呢?
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Xilinx Employee
Xilinx Employee
405 次查看
注册日期: ‎05-15-2008

Can you compare the messages in the tcl console in 2018.2 with the ones in 2019.2?

What is the next step after "export_simulation" in 2018.2?

This may help to determine which step caused the halting.

Regarding the "Design Runs" tab, I'm not referring to the "synth" run, but the "Out-of-context module runs".

When the tool is generating output product for the BD, it actually launches OOC synth runs for each IP in the BD.

Can you expand the arrow before "system" under the "Out-of-context module runs" (you may need to do this before it halts) and check if all runs under it completed. If some failed or even not started when the halting happen, check the log file of that run (you can find the log in a folder in xxxx.runs directory). You can post the log file. Please do not paste all the contents in the log file but just attach the log file in the attachment.

-vivian

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在原帖中查看解决方案

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Xilinx Employee
Xilinx Employee
699 次查看
注册日期: ‎05-15-2008

Vivado卡死的具体现象是什么呢?GUI界面的截图提供一下吧

tcl console里打印的信息有哪些?

有没有弹出什么窗口信息?

使用的什么操作系统呢?

描述问题请尽量详细

如果可以的话请提供复现问题的工程。

另外可以试一下2020.1

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Visitor
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686 次查看
注册日期: ‎07-01-2020

你好!

使用的操作系统是win10专业版

Vivado软件版本是2019.2

新建任何Vivado工程执行Generate Output Product都会卡死,没有任何弹窗。

附件是Vivado界面卡死后的截图。

以下是软件卡死前,tcl console里打印的信息:

start_gui
open_project E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.xpr
WARNING: [Board 49-69] Validation failed for board file C:/Xilinx/Vivado/2019.2/data/boards/board_files/PYNQ-Z2/A.0/board.xml:
Frequency Parameter not provided for audio_clock

open_project E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.xpr
WARNING: [Board 49-69] Validation failed for board file C:/Xilinx/Vivado/2019.2/data/boards/board_files/PYNQ-Z2/A.0/board.xml:
Frequency Parameter not provided for audio_clock

Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.2/data/ip'.
open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 842.508 ; gain = 165.504
update_compile_order -fileset sources_1
reset_project
open_bd_design {E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd}
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block!
Successfully read diagram <system> from BD file <E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd>
open_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 961.777 ; gain = 83.805
reset_target all [get_files E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd]
export_ip_user_files -of_objects [get_files E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd] -sync -no_script -force -quiet
delete_ip_run [get_files -of_objects [get_fileset sources_1] E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd]
generate_target all [get_files E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd]
INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run.
Wrote : <E:\Project\HokeProject\LDCU2\BoardTest\project_2\project_2.srcs\sources_1\bd\system\system.bd>
VHDL Output written to : E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/synth/system.v
VHDL Output written to : E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/sim/system.v
VHDL Output written to : E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/hdl/system_wrapper.v
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
Exporting to file E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/hw_handoff/system.hwh
Generated Block Design Tcl file E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
Generated Hardware Definition File E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/synth/system.hwdef
generate_target: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1156.891 ; gain = 172.727
catch { config_ip_cache -export [get_ips -all system_processing_system7_0_0] }
export_ip_user_files -of_objects [get_files E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd]
launch_runs -jobs 4 system_processing_system7_0_0_synth_1
[Fri Jul 3 12:41:52 2020] Launched system_processing_system7_0_0_synth_1...
Run output will be captured here: E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.runs/system_processing_system7_0_0_synth_1/runme.log
export_simulation -of_objects [get_files E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.srcs/sources_1/bd/system/system.bd] -directory E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.ip_user_files/sim_scripts -ip_user_files_dir E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.ip_user_files -ipstatic_source_dir E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.ip_user_files/ipstatic -lib_map_path [list {modelsim=E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.cache/compile_simlib/modelsim} {questa=E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.cache/compile_simlib/questa} {riviera=E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.cache/compile_simlib/riviera} {activehdl=E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet

Vivado卡死界面.png
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Xilinx Employee
Xilinx Employee
662 次查看
注册日期: ‎05-15-2008

2019.2新安装的吗?还是以前是好的?

1. 2019.2 支持的win10操作系统具体要求如下,请检查一下你的win 10是否符合?

Microsoft Windows 10.0 1809 Update; 10.0 1903 Update (64-bit), English/Japanese

2. 是否有内存不够用的可能可能存在?

3. E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.runs/system_processing_system7_0_0_synth_1/runme.log

这个log文件找出来看看,可以贴上来

4. 工程所在的目录有点深,尝试缩短目录看看

5. E:/Project/HokeProject/LDCU2/BoardTest/project_2/project_2.ip_user_files/sim_scripts这个目录下看看是否有仿真脚本等文件产生(发生故障前最后一个命令是export_simulation

6. 有条件的话可以试一下2020.1

-vivian

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Visitor
Visitor
460 次查看
注册日期: ‎07-01-2020

Viviany, 你好!

按你的建议我做了如下修改后,Vivado仍然在Generate Output Product时卡死:

1. 升级到Vivado 2020.1,并卸载了Vivado 2019.2 ;

2. 重新新建工程目录为:E:/ExerciseBook/ExerciseForM70X0/Ex1;

3. 监测内存使用并没耗尽内存;

以下为Vivado 2020.1卡死界面+内存监测与WIN10版本截图。

Vivado卡死界面+内存监测.pngWIN10系统版本.png

以下是工程运行的log信息(目录为E:\ExerciseBook\ExerciseForM70X0\Ex1\Ex1.runs\system_processing_system7_0_0_synth_1\runme.log):


*** Running vivado
with args -log system_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_processing_system7_0_0.tcl

 

****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source system_processing_system7_0_0.tcl -notrace
Command: synth_design -top system_processing_system7_0_0 -part xc7z020clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 11020
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1070.531 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer
Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer
Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer
Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer
Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer
Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer
Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer
Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string
Parameter C_FCLK_CLK1_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK2_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string
Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer
Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer
Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer
Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer
Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer
Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string
Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer
Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer
Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer
Parameter C_DQ_WIDTH bound to: 32 - type: integer
Parameter C_DQS_WIDTH bound to: 4 - type: integer
Parameter C_DM_WIDTH bound to: 4 - type: integer
Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer
Parameter C_PACKAGE_NAME bound to: clg400 - type: string
Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string
Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer
Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer
Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer
Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer
Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer
Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 1 - type: integer
Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'BUFG' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (2#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6157] synthesizing module 'PS7' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'PS7' (3#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (4#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (5#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1089.367 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
Finished Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_processing_system7_0_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.938 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1122.906 ; gain = 3.969
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for inst. (constraint file E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1308.949 ; gain = 238.418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1328.832 ; gain = 258.301
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.289 ; gain = 272.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |BIBUF | 130|
|2 |BUFG | 1|
|3 |LUT1 | 112|
|4 |PS7 | 1|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1348.297 ; gain = 236.598
Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1348.297 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1370.066 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1370.066 ; gain = 299.535
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP system_processing_system7_0_0, cache-ID = 42748ae7508352cd
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_processing_system7_0_0_utilization_synth.rpt -pb system_processing_system7_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Jul 4 22:05:39 2020...

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注册日期: ‎07-01-2020

Viviany, 你好!

按你的建议我做了如下修改后,Vivado仍然在Generate Output Product时卡死:

1. 升级到Vivado 2020.1,并卸载了Vivado 2019.2 ;

2. 重新新建工程目录为:E:/ExerciseBook/ExerciseForM70X0/Ex1;

3. 监测内存使用并没耗尽内存;

以下为Vivado 2020.1卡死界面+内存监测与WIN10版本截图。

Vivado卡死界面+内存监测.pngWIN10系统版本.png

以下是工程运行的log信息(目录为E:\ExerciseBook\ExerciseForM70X0\Ex1\Ex1.runs\system_processing_system7_0_0_synth_1\runme.log):


*** Running vivado
with args -log system_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_processing_system7_0_0.tcl


****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source system_processing_system7_0_0.tcl -notrace
Command: synth_design -top system_processing_system7_0_0 -part xc7z020clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 11020
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1070.531 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer
Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer
Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer
Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer
Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer
Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer
Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer
Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string
Parameter C_FCLK_CLK1_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK2_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string
Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer
Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer
Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer
Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer
Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer
Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string
Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer
Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer
Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer
Parameter C_DQ_WIDTH bound to: 32 - type: integer
Parameter C_DQS_WIDTH bound to: 4 - type: integer
Parameter C_DM_WIDTH bound to: 4 - type: integer
Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer
Parameter C_PACKAGE_NAME bound to: clg400 - type: string
Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string
Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer
Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer
Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer
Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer
Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer
Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 1 - type: integer
Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'BUFG' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (2#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6157] synthesizing module 'PS7' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'PS7' (3#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (4#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (5#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1089.367 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
Finished Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_processing_system7_0_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.938 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1122.906 ; gain = 3.969
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for inst. (constraint file E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1308.949 ; gain = 238.418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1328.832 ; gain = 258.301
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.289 ; gain = 272.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |BIBUF | 130|
|2 |BUFG | 1|
|3 |LUT1 | 112|
|4 |PS7 | 1|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1348.297 ; gain = 236.598
Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1348.297 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1370.066 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1370.066 ; gain = 299.535
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP system_processing_system7_0_0, cache-ID = 42748ae7508352cd
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_processing_system7_0_0_utilization_synth.rpt -pb system_processing_system7_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Jul 4 22:05:39 2020...

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注册日期: ‎07-01-2020

Viviany, 你好!

按你的建议我做了如下修改后,Vivado仍然在Generate Output Product时卡死:

1. 升级到Vivado 2020.1,并卸载了Vivado 2019.2 ;

2. 重新新建工程目录为:E:/ExerciseBook/ExerciseForM70X0/Ex1;

3. 监测内存使用并没耗尽内存;

4. 系统版本为:Windows 10 专业版64位(10.0, 版本 18362)。

附件为Vivado 2020.1卡死界面+内存监测截图。

 

以下是工程运行的log信息(目录为E:\ExerciseBook\ExerciseForM70X0\Ex1\Ex1.runs\system_processing_system7_0_0_synth_1\runme.log):


*** Running vivado
with args -log system_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_processing_system7_0_0.tcl


****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source system_processing_system7_0_0.tcl -notrace
Command: synth_design -top system_processing_system7_0_0 -part xc7z020clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 11020
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1070.531 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer
Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer
Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer
Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer
Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer
Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer
Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer
Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string
Parameter C_FCLK_CLK1_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK2_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string
Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer
Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer
Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer
Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer
Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer
Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string
Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer
Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer
Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer
Parameter C_DQ_WIDTH bound to: 32 - type: integer
Parameter C_DQS_WIDTH bound to: 4 - type: integer
Parameter C_DM_WIDTH bound to: 4 - type: integer
Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer
Parameter C_PACKAGE_NAME bound to: clg400 - type: string
Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string
Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer
Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer
Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer
Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer
Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer
Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 1 - type: integer
Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'BUFG' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (2#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6157] synthesizing module 'PS7' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'PS7' (3#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (4#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (5#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1089.367 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
Finished Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_processing_system7_0_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.938 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1122.906 ; gain = 3.969
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for inst. (constraint file E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1308.949 ; gain = 238.418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1328.832 ; gain = 258.301
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.289 ; gain = 272.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |BIBUF | 130|
|2 |BUFG | 1|
|3 |LUT1 | 112|
|4 |PS7 | 1|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1348.297 ; gain = 236.598
Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1348.297 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1370.066 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1370.066 ; gain = 299.535
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP system_processing_system7_0_0, cache-ID = 42748ae7508352cd
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_processing_system7_0_0_utilization_synth.rpt -pb system_processing_system7_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Jul 4 22:05:39 2020...

Vivado卡死界面+内存监测.png
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注册日期: ‎07-01-2020

Viviany, 你好!

按你的建议我做了如下修改后,Vivado仍然在Generate Output Product时卡死:

1. 升级到Vivado 2020.1,并卸载了Vivado 2019.2 ;

2. 重新新建工程目录为:E:/ExerciseBook/ExerciseForM70X0/Ex1;

3. 监测内存使用并没耗尽内存;

附件为Vivado 2020.1卡死界面+内存监测与WIN10版本截图。

 

以下是工程运行的log信息(目录为E:\ExerciseBook\ExerciseForM70X0\Ex1\Ex1.runs\system_processing_system7_0_0_synth_1\runme.log):


*** Running vivado
with args -log system_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_processing_system7_0_0.tcl


****** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:49 MDT 2020
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source system_processing_system7_0_0.tcl -notrace
Command: synth_design -top system_processing_system7_0_0 -part xc7z020clg400-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 11020
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1070.531 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer
Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer
Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer
Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer
Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer
Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer
Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer
Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string
Parameter C_FCLK_CLK1_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK2_BUF bound to: FALSE - type: string
Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string
Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer
Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer
Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer
Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer
Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer
Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string
Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer
Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer
Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer
Parameter C_DQ_WIDTH bound to: 32 - type: integer
Parameter C_DQS_WIDTH bound to: 4 - type: integer
Parameter C_DM_WIDTH bound to: 4 - type: integer
Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer
Parameter C_PACKAGE_NAME bound to: clg400 - type: string
Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string
Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer
Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer
Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer
Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer
Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer
Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 1 - type: integer
Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'BUFG' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (2#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:730]
INFO: [Synth 8-6157] synthesizing module 'PS7' [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'PS7' (3#1) [D:/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:62027]
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (4#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (5#1) [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:60]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1081.738 ; gain = 11.207
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1089.367 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
Finished Parsing XDC File [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [e:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_processing_system7_0_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1118.938 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1122.906 ; gain = 3.969
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for inst. (constraint file E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1122.906 ; gain = 52.375
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1308.949 ; gain = 238.418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1328.832 ; gain = 258.301
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.289 ; gain = 272.758
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |BIBUF | 130|
|2 |BUFG | 1|
|3 |LUT1 | 112|
|4 |PS7 | 1|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1348.297 ; gain = 236.598
Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 1348.297 ; gain = 277.766
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1348.297 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1370.066 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1370.066 ; gain = 299.535
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP system_processing_system7_0_0, cache-ID = 42748ae7508352cd
INFO: [Common 17-1381] The checkpoint 'E:/ExerciseBook/ExerciseForM70X0/Ex1/Ex1.runs/system_processing_system7_0_0_synth_1/system_processing_system7_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_processing_system7_0_0_utilization_synth.rpt -pb system_processing_system7_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Jul 4 22:05:39 2020...

Vivado卡死界面+内存监测.png
WIN10系统版本.png
0 项奖励
Highlighted
Xilinx Employee
Xilinx Employee
499 次查看
注册日期: ‎05-15-2008

建议的第5条是否有检查?

从synth的log看,综合正常结束了。

在design runs选项卡里看一下,这个bd一共有多少synth run启动?

如果前端的进度条从一开始就点“Background”的话,是否有变化?

新改的工程路径还是挺长的,不过不确定是否是路径长的原因,只是一种猜测,实在是没什么线索。。。

另外可以尝试用命令行去跑,不用GUI,看是否能完成。如果命令行能完成可以对比下命令行的log和GUI tcl console的log看是否有新的线索

-vivian

 

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Visitor
Visitor
449 次查看
注册日期: ‎07-01-2020

建议第5条的仿真脚本是下面这个simulate.do文件吗?

vivado卡死截图1.png

在design runs选项卡里看了,bd下只有一个synth,并没有启动综合?

vivado卡死截图.png

如果前端的进度条从一开始就点“Background”的话,是否有变化?-------还没卡死前点“Background”,没有变化,界面一样会卡死,Tcl  Console显示信息一样。

命令行执行什么命令呢?能发一下相应的命令吗?

至于路径长短的问题,我认为不是造成Vivado卡死的原因。用Vivado2018.2版本在同样的路径下新建工程,执行同样的操作,Vivado2018.2完全能正常运行。

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Xilinx Employee
Xilinx Employee
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注册日期: ‎05-15-2008

Can you compare the messages in the tcl console in 2018.2 with the ones in 2019.2?

What is the next step after "export_simulation" in 2018.2?

This may help to determine which step caused the halting.

Regarding the "Design Runs" tab, I'm not referring to the "synth" run, but the "Out-of-context module runs".

When the tool is generating output product for the BD, it actually launches OOC synth runs for each IP in the BD.

Can you expand the arrow before "system" under the "Out-of-context module runs" (you may need to do this before it halts) and check if all runs under it completed. If some failed or even not started when the halting happen, check the log file of that run (you can find the log in a folder in xxxx.runs directory). You can post the log file. Please do not paste all the contents in the log file but just attach the log file in the attachment.

-vivian

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在原帖中查看解决方案

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Visitor
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注册日期: ‎07-01-2020

Thanks for your answer.

I have sloved this problem by refreshing my win10 opreating system.

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