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Adah
Visitor
Visitor
342 次查看
注册日期: ‎04-02-2021

creat hdl wrapper

creat hdl wrapper时遇到下列错误,希望能得到大家的帮助

[BD 41-758] The following clock pins are not connected to a valid clock source:
/processing_system7_0/M_AXI_GP0_ACLK

[BD 41-1031] Hdl Generation failed for the IP Integrator design D:/PYNQ/OFDM/vivadofft/project_2/project_2.srcs/sources_1/bd/design_1/design_1.bd

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Hrishikesh
Adventurer
Adventurer
339 次查看
注册日期: ‎09-26-2020

Hello,

You need to connect the FCLK_CLK0 to all the clk ports, you also should complete the design before you go for creation of HDL Wrapper.

1. Complete all connections 

2. Validate design to make sure there are no problems

3. Generate Output products

4. Create HDL Wrapper

Try Following this sequence.

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Adah
Visitor
Visitor
322 次查看
注册日期: ‎04-02-2021

你好,连了clk之后,出现了critical warning,如下

[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/fft_top_0/direction_ap_vld
/fft_top_0/direction
/fft_top_0/ap_start

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Love24
Explorer
Explorer
319 次查看
注册日期: ‎10-22-2020

看你的电路图,M_AXI_GP0这组AXI总线没有用到,可以直接不勾选它,这样的话就不会有GP0_ACLK这个端口了,这个端口提供的时钟就是给AXI总线用的。

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Adah
Visitor
Visitor
310 次查看
注册日期: ‎04-02-2021

请问在哪取消勾选呢

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Love24
Explorer
Explorer
307 次查看
注册日期: ‎10-22-2020

双击ZYNQ框,进入配置界面,PS-PL configuration→AXI Non Secure Enablement→GP master AXI interface,取消勾选GP0即可

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Adah
Visitor
Visitor
286 次查看
注册日期: ‎04-02-2021

这个问题已经解决,谢谢

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