修改时间 04-02-2021 03:11 PM
creat hdl wrapper时遇到下列错误，希望能得到大家的帮助
[BD 41-758] The following clock pins are not connected to a valid clock source:
[BD 41-1031] Hdl Generation failed for the IP Integrator design D:/PYNQ/OFDM/vivadofft/project_2/project_2.srcs/sources_1/bd/design_1/design_1.bd
修改时间 04-02-2021 03:15 PM
You need to connect the FCLK_CLK0 to all the clk ports, you also should complete the design before you go for creation of HDL Wrapper.
1. Complete all connections
2. Validate design to make sure there are no problems
3. Generate Output products
4. Create HDL Wrapper
Try Following this sequence.
修改时间 04-02-2021 03:27 PM
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: