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Visitor
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注册日期: ‎12-06-2018

place_design error for solution

i'm a beginner

i just tried a exercise,but it failed.

 [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] >

clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y163
and clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

 I do this as it described 

As follow 

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE FALSE[get_nets clk_i]
create_clock -period 10.000 -name clk_i -waveform {0.000 5.000} -add [get_ports clk]

but it's of no use 

what should i do?

 

 

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Xilinx Employee
Xilinx Employee
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回复: place_design error for solution

关于此错误信息,请参考以下Answer:

https://www.xilinx.com/support/answers/64452.html

一般是未放到时钟专用管脚,或者放到了时钟专用差分输入管脚的_N。

注意到你加的CLOCK_DEDICATED_ROUTE约束是应用在了get_nets clk_i,而非错误信息建议的clk_IBUF。请按照提示的约束进行修改,此属性需要设置在IBUF输出信号上。

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Visitor
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回复: place_design error for solution

你好 
我改了

改成了 get nets clk_IBUF.但是问题没解决。

我编的程序是最简单的那种,是一个入门教程上的程序。我着实弄不懂这是为啥

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Xilinx Employee
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回复: place_design error for solution

请问你用的是哪个Vivado版本?使用的例程能附上吗?

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回复: place_design error for solution

我用的vivado2018.2

xdc

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE FALSE[get_nets clk_IBUF]
create_clock -period 10.000 -name clk_i -waveform {0.000 5.000} -add [get_ports clk]

set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports led]

就这四个

然后design source

`timescale 1ns / 1ps

module exercise(
input clk,
output led
);
reg [24:0] count = 0;

assign led = count[24];

always @ (posedge(clk)) count <= count + 1;
endmodule

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回复: place_design error for solution

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Xilinx Employee
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回复: place_design error for solution

按照你提供的链接创建工程,并未复现你的错误。

请确认你选择的是Digilent的那块板子?如按照链接所示,选择Zybo的话,clk管脚对应的位置应为L16。

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回复: place_design error for solution

我用的不是链接的那块板子
我用的a7 100T 那块板子  clk管脚应该是E3好像
但是我不太懂换了一块板子一个很简单的编程就会出现错误了吗
不应该这个程序对于所有板子都应该适用吗?最多就是管脚不同,然后xdc里面有些小小的差异吧

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Xilinx Employee
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回复: place_design error for solution

不同的封装,时钟专用管脚对应的IO位置是不一样的,不兼容的两个器件不能直接沿用原来的IO约束。

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Visitor
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回复: place_design error for solution

这个我明白  所以我在A7 100T上 clk管脚是它的专用管脚 e3   led也是它的管脚  
然后我source design 没变  ,constrains source 只是因为封装不同管脚,电压什么的不同了  其他都没变
这样也会引起不同板子就会有错误吗

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Xilinx Employee
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回复: place_design error for solution

如果是同样的源文件,请告知你的具体器件封装以及更新后的XDC。对于专用的时钟管脚来说,不会出现以上错误。

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Visitor
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回复: place_design error for solution

抱歉这么久才回复

我的vivado版本2018.2    板子是A7 100T

我的xdc文件

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE FALSE[get_nets clk_IBUF]
create_clock -period 10.000 -name clk_i -waveform {0.000 5.000} -add [get_ports clk]

set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports led]

就这四个

然后design source

`timescale 1ns / 1ps

module exercise(
input clk,
output led
);
reg [24:0] count = 0;

assign led = count[24];

always @ (posedge(clk)) count <= count + 1;
endmodule

 

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Xilinx Employee
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回复: place_design error for solution

A7 100T具体什么封装?

在工程的Package Pins Window中查看E3,是时钟专用输入管脚(SRCC/MRCC)吗?

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Visitor
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回复: place_design error for solution

您好,麻烦了
我查看了我觉得是的吧(不敢肯定),因为我看很多demo什么的都是E3管脚
我的文件压缩在附件里面了。麻烦您帮我看看
真的谢谢你了

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