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Visitor
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注册日期: ‎01-18-2017

vivado综合乘法器和移位出错,求解

在vivado中综合如下的代码时出现了错误:c_ref寄存器始终为0,而c_ref_temp的寄存器有值。

 reg   [30:0]   c_ref;

 wire  [32:0]   c_ref_temp = small_n * htotal_temp;

 always@(posedge ad_osc_27m_ck_int_fll or negedge glb_rst_n)

 if(!glb_rst_n)

    c_ref  <= 'd0;

 else

   c_ref  <= c_ref_temp[31:1];

 通过打开综合后的Netlist观察,发现输入复位glb_rst_n直接连接到了寄存器c_ref的RESET端,导致c_ref始终为0(glb_rst_n为低电平有效,正常运行状态为高,正好复位住寄存器)。

综合成的网表如下图所示,由于寄存器的CLR端是高电平有效,而外部输入的glb_rst_n为低电平有效,正常状态下为高,从而导致正常工作时,寄存器一直处于复位状态,输出一直位0

net.PNG

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Xilinx Employee
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回复: vivado综合乘法器和移位出错,求解

Where did you observe that the the c_ref is always 0? In simulation or HW testing?

Would you provide the screenshot of the post-synthesis schematic of this register, rather than a manually created diagram?

Please also check the pin property of the CLR pin. Is the "is_inverted" property ON? If so, that means the glb_rst_n is low active.

-vivian

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回复: vivado综合乘法器和移位出错,求解

I observe that c_ref is always 0 in HW Testing.

The screenshot of the post-synthesis schematic of this register  below:

And glb_rst_n is active low.

schmatic_副本.png 

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Xilinx Employee
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回复: vivado综合乘法器和移位出错,求解

The screenshot is not clear enough to show the c_ref register.

Have you checked the "is_inverted" property of the CLR pin? If it is ON, the register is correctly inferred.

I suggest you run simulation to check the register's value.

-vivian

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回复: vivado综合乘法器和移位出错,求解

I checked the "is_inverted" property of the CLR pin and it is OFF.

CLR PIN.PNG

c_ref和c_ref_temp的schematic 截屏见下图:

c_ref_temp.PNG

c_ref寄存器的名字在综合后变为c_ref_reg.

c_ref.PNG

再次跑了仿真。behavioral simulation的结果是对的,见下图

behiver_simlation.PNG

post-synthesis 仿真后的结果是错的,见下图:

post_synthesis_simulation.PNG

if possible, You can write similar code and run synthesis for check. 

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Xilinx Employee
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回复: vivado综合乘法器和移位出错,求解

Please manually change the is_inverted property of the CLR pin to ON, save the change in the synthesized design. And then test it.

I'm afraid the issue might not be able to reproduced with a simple test case.

Can you reproduce the issue with the file in which c_ref is described as top module and run Synthesis?

-vivian

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Visitor
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回复: vivado综合乘法器和移位出错,求解

I changed the  "is_inverted"  property of the CLR pin to ON. But when I re-synthesis the project and re-open  synthesized Design

The  "is_inverted"  property of the CLR pin  is backto OFF.

I am sure the issue could be reproduced in top module and the issue is stable.

You can input the following code ,then synthesis and open the synthesized design, you can find the issue.

module c_ref_top(
   input wire  gclk1,
   input wire  glb_rst_n,
   input wire  [16:0]  small_n,
   input wire  [15:0]  htotal_temp,
   output  reg [30:0] result_out
);

wire gclk_prog_bg;

BUFG u_bufg_gclk
(
  .O(gclk_prog_bg),
.I(gclk1)
);

reg [30:0] c_ref;
wire [32:0] c_ref_temp = small_n * htotal_temp;

always@(posedge gclk_prog_bg or negedge glb_rst_n)
begin
if(glb_rst_n == 1'b0)
c_ref <= 'd0;
else
c_ref <= c_ref_temp[31:1];
end

always@(posedge gclk_prog_bg or negedge glb_rst_n)
begin
if(glb_rst_n == 1'b0)
result_out <= 31'd0;
else
result_out <= c_ref;
end

endmodule

 

And My project Device is xcvu9p-flga2104-2-i

My vivado version is 2018.3

thanks

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Xilinx Employee
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回复: vivado综合乘法器和移位出错,求解

Will try and let you know.

Thanks

-vivian

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Xilinx Employee
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回复: vivado综合乘法器和移位出错,求解

在2020.1上综合结果,可以的话升级一下版本试试看。

Capture.PNG

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回复: vivado综合乘法器和移位出错,求解

看到综合后的结果是寄存器result_out_reg的CLR端连接为glb_rst_n的取反。

在vivado2018.3中result_out_reg的CLR端也是glb_rst_n的取反。

需要再看下result_out_reg的前一级寄存器(在vivado2018.3中综合后的名字为p_0_out)的CLR端是否是直连到glb_rst_n。

(p_0_out寄存器的D端为 c_ref_temp , Q端为c_ref_reg)

谢谢!

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回复: vivado综合乘法器和移位出错,求解

你好!

图中给出schematic为寄存器result_out_reg的CLR端连接为glb_rst_n的取反。

在vivado 2018.3综合后result_out_reg的CLR也是连接到glb_rst_n的取反,只是result_out_reg的前级寄存器p_0_out(在vivado 2018.3综合后的命名)的CLR端直连到glb_rst_n,导致c_ref的值恒为0。其中p_0_out的D端为输入net为c_ref_temp,Q端输出为c_ref_reg。

烦请看下vivado 2020.1中综合后的p_0_out寄存器的CLR端(在vivado 2020.1中p_0_out的值有可能会改变,但是其输入D端为c_ref_temp,Q端输出为c_ref_reg)

谢谢!

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回复: vivado综合乘法器和移位出错,求解

是的,2020.1的结果是正确的。

单独综合这个文件的综合结果,跟你的稍有不同,result_out_reg的前一级寄存器命名不一样,在2020.1里面,所有寄存器都是glb_rst_n取反后连接到CLR的。

请使用2020.1试一下

-vivian

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回复: vivado综合乘法器和移位出错,求解

好的,我们尝试下。请问下vivado 2020.1的版本从哪里可以下载到?

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Xilinx Employee
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回复: vivado综合乘法器和移位出错,求解

官网上有:

https://www.xilinx.com/support/download.html

-vivian

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