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Adah
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注册日期: ‎04-02-2021

vivado自定义ip

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自定义IP连接时出现以下警告,麻烦各位帮忙,感谢

[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/fft_top_0/direction_ap_vld
/fft_top_0/direction
/fft_top_0/ap_start

捕获.PNG

捕获1.PNG

 

 

 

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1 解答

已接受的解答
graces
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300 次查看
注册日期: ‎07-17-2008

这些是IP的顶层输入管脚啊,跟IP内部逻辑无关,你要在Block Design里面做连接。

就像你RTL顶层例化子模块,子模块的输入悬空是一样的道理。

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

在原帖中查看解决方案

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graces
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Moderator
335 次查看
注册日期: ‎07-17-2008

如字面意思,自定义IP的这些输入管脚是悬空未连接的,工具会自动把它们接地。

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
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Adah
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注册日期: ‎04-02-2021

那请问要怎么解决呢?它显示是critical warning

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graces
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注册日期: ‎07-17-2008

如果接地与实际不符,那用户需要去把该接的输入端口都连接完整。

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
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Adah
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注册日期: ‎04-02-2021

需要在IP核的程序里面去改吗?还是直接在vivado里面连接就可以呢

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graces
Moderator
Moderator
301 次查看
注册日期: ‎07-17-2008

这些是IP的顶层输入管脚啊,跟IP内部逻辑无关,你要在Block Design里面做连接。

就像你RTL顶层例化子模块,子模块的输入悬空是一样的道理。

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

在原帖中查看解决方案

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Adah
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299 次查看
注册日期: ‎04-02-2021

喔喔,好的,谢谢

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