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Visitor
Visitor
8,051 Views
Registered: ‎10-24-2013

4 bit binary counter

Hi there,

 

I need to make a test bench waveform of a 4 bit binary counter, CB4CE. Im really new to all this, and dont really understand how to make the test bench waveform correctly. I understand how the counter works but dont know how to program it. According to the task we have to make a schematic first, which I did and then the test bench waveform and a simulation. this is what I got;

tb : PROCESS
BEGIN
CEO <='0'; TC <='0'; CLR <='0'; CE <='0'; CLK <='0000'; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0001'; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0010'; Q0 <='0'; Q1 <='0'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0011'; Q0 <='0'; Q1 <='0'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0100'; Q0 <='0'; Q1 <='1'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0101'; Q0 <='0'; Q1 <='1'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0110'; Q0 <='0'; Q1 <='1'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0111'; Q0 <='0'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1000'; Q0 <='1'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1001'; Q0 <='1'; Q1 <='0'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1010'; Q0 <='1'; Q1 <='0'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1011'; Q0 <='1'; Q1 <='0'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1100'; Q0 <='1'; Q1 <='1'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1101'; Q0 <='1'; Q1 <='1'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1110'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1111'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='1'; TC <='1'; CLR <='0'; CE <='1'; CLK <='1111'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='1'; CLR <='0'; CE <='1'; CLK <='1111'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='1'; CE <='0'; CLK <='0000'; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;

END PROCESS;

 

The errors I get are like this Line ..:Syntax error near "'".

I know Im way off on this one, can someone tell me what im doing wrong? if someone could point me the right direction would be really helpful. Any advice is welcome.

Thanks!!

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7 Replies
Xilinx Employee
Xilinx Employee
8,045 Views
Registered: ‎07-11-2011

Hi,

 

I think you need not have a colon before wait

Please see below link for correct syntax or refer language templates in ISE/Vivado.

 

http://vhdl.renerta.com/mobile/source/vhd00081.htm

 

Hope this helps.

 

Regards,

Vanitha.

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Teacher
Teacher
8,037 Views
Registered: ‎09-09-2010

All of the CLK assignments are invalid VHDL:
CLK <='0000';
If CLK is indeed a 4-bit vector it should be
CLK <="0000"; -- etc.

If you don't want the process to repeat, you need
WAIT;
before 'END PROCESS'

However, that style is utterly horrible, IMHO.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Scholar
Scholar
8,035 Views
Registered: ‎06-05-2013

Hi,

You are assigning CLK <='0000'; but it should be in double quotes. CLK <="0000"

Regards,
Pratham
-Pratham

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Visitor
Visitor
8,025 Views
Registered: ‎10-24-2013

Thanks for the replies everyone, I assigned CLK in double quotes as you guys suggested but I still get the same errors.

Hahaha my teacher told me something similar about my style of doing it too. As far as I know the CLK starts counting when CE is high, thats why I put ; 

CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0001'; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0010'; Q0 <='0'; Q1 <='0'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0011'; Q0 <='0'; Q1 <='0'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0100'; Q0 <='0'; Q1 <='1'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0101'; Q0 <='0'; Q1 <='1'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0110'; Q0 <='0'; Q1 <='1'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='0111'; Q0 <='0'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1000'; Q0 <='1'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1001'; Q0 <='1'; Q1 <='0'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1010'; Q0 <='1'; Q1 <='0'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1011'; Q0 <='1'; Q1 <='0'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1100'; Q0 <='1'; Q1 <='1'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1101'; Q0 <='1'; Q1 <='1'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1110'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <='1111'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;

 

If CE is low than CLK doesn't count, so I put; CEO <='0'; TC <='0'; CLR <='0'; CE <='0'; CLK <='0000'; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;

 

TC is high when all the Q's are high; CEO <='0'; TC <='1'; CLR <='0'; CE <='1'; CLK <='1111'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;

 

CEO is high when TC and CE are high; CEO <='1'; TC <='1'; CLR <='0'; CE <='1'; CLK <='1111'; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;

 

And if CLR is high all other inputs and outputs are low; CEO <='0'; TC <='0'; CLR <='1'; CE <='0'; CLK <='0000'; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns

 

This what I could understand about the working of the counter when you press on ''symbol info'' on the schematic. 

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Scholar
Scholar
8,010 Views
Registered: ‎06-05-2013

Hi,

What are you trying to achieve? please post your entire code.
-Pratham

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Visitor
Visitor
8,005 Views
Registered: ‎10-24-2013

Im trying to make a test bench waveform and then I want to simulate the design. 

This is the enitre code; 

 

COMPONENT Proef4
PORT( CE : IN STD_LOGIC;
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
TC : OUT STD_LOGIC;
CEO : OUT STD_LOGIC;
Q3 : OUT STD_LOGIC;
Q2 : OUT STD_LOGIC;
Q1 : OUT STD_LOGIC;
Q0 : OUT STD_LOGIC);
END COMPONENT;

 

SIGNAL CE : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
SIGNAL CLR : STD_LOGIC;
SIGNAL TC : STD_LOGIC;
SIGNAL CEO : STD_LOGIC;
SIGNAL Q3 : STD_LOGIC;
SIGNAL Q2 : STD_LOGIC;
SIGNAL Q1 : STD_LOGIC;
SIGNAL Q0 : STD_LOGIC;

 

BEGIN

 

UUT: Proef4 PORT MAP(
CE => CE,
CLK => CLK,
CLR => CLR,
TC => TC,
CEO => CEO,
Q3 => Q3,
Q2 => Q2,
Q1 => Q1,
Q0 => Q0
);

-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
CEO <='0'; TC <='0'; CLR <='0'; CE <='0'; CLK <=''0000''; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0001''; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0010''; Q0 <='0'; Q1 <='0'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0011''; Q0 <='0'; Q1 <='0'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0100''; Q0 <='0'; Q1 <='1'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0101''; Q0 <='0'; Q1 <='1'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0110''; Q0 <='0'; Q1 <='1'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''0111''; Q0 <='0'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1000''; Q0 <='1'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1001''; Q0 <='1'; Q1 <='0'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1010''; Q0 <='1'; Q1 <='0'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1011''; Q0 <='1'; Q1 <='0'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1100''; Q0 <='1'; Q1 <='1'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1101''; Q0 <='1'; Q1 <='1'; Q2 <='0'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1110''; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='0'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='0'; CE <='1'; CLK <=''1111''; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='1'; TC <='1'; CLR <='0'; CE <='1'; CLK <=''1111''; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='1'; CLR <='0'; CE <='1'; CLK <=''1111''; Q0 <='1'; Q1 <='1'; Q2 <='1'; Q3 <='1'; WAIT for 40 ns;
CEO <='0'; TC <='0'; CLR <='1'; CE <='0'; CLK <=''0000''; Q0 <='0'; Q1 <='0'; Q2 <='0'; Q3 <='0'; WAIT for 40 ns;

END PROCESS;


-- *** End Test Bench - User Defined Section ***

END;

 

Thanks!

 

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Scholar
Scholar
7,993 Views
Registered: ‎06-05-2013

Hello,

Your clock is of one bit then why are you assigning 4 bit value to it.
You should write separate process to generate clock.
-Pratham

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