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taghlaoui
Visitor
Visitor
2,247 Views
Registered: ‎04-28-2014

A bitstream will not be generated

Hi

I'm working on loadin unix on FPGA , firstly I'm using EDK 13.4 on ubuntu 12.04 , the problem is when i try to generate the bitstream I get that message

 

ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0
********************************************************************************
Analyzing implementation/system.par
make: *** [implementation/system.bit] Erreur 1
Done!

PLease I need help

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2 Replies
vijayak
Xilinx Employee
Xilinx Employee
2,236 Views
Registered: ‎10-24-2013

Hi,

Please check this thread where similar topic is discussed.
http://forums.xilinx.com/t5/Embedded-Development-Tools/PAR-could-not-meet-all-timing-constraints-when-xps-hwicap-5-01-a/td-p/177122
Thanks,Vijay
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vijayak
Xilinx Employee
Xilinx Employee
2,218 Views
Registered: ‎10-24-2013

@taghlaoui Did the above post solved your issue? If yes please close the thread by marking as solution.
Thanks,Vijay
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