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Visitor
Visitor
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Registered: ‎08-15-2013

AC701 Development Board clock mapping

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Hi everyone,

 

I am new to FPGA programming, and my team purchased an Artix 7 development board (xc7a200t-2fbg676) to experiment with. I have been bringing myself up to speed with various online tutorials, but I am now stuck when I have to connect a clock input in my UCF file. In all of the boards the tutorial authors use, it is as simple as adding:

 

NET "clk" LOC = A8;

 

or something similar. In the course of my research, I now know that the Artix 7 uses a differential clock involving two pins, instead of one clock pin. I have done my due diligence on Google and in these forums for the last three days, and I keep coming up dry. Can someone please explain to me how to connect the internal clock on the AC701 development board through the UCF?

 

Many thanks,

Grant

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Visitor
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Registered: ‎08-15-2013

I can't thank you enough for your help, Austin.

 

So that no one else has to spend the time I did scouring the internet for this information, I figure I'll post my solution for anyone else who wants to turn the differential clock into a single-input clock (without changing the frequency).

 

In the UCF file:

 

NET "CLK_P" LOC = "R3" | IOSTANDARD = "DIFF_SSTL15";

NET "CLK_N" LOC = "P3" | IOSTANDARD = "DIFF_SSTL15";

 

Then in my schematic file, I wired CLK_P and CLK_N into an IBUFGDS module, and then wired that into a BUFG module.

 

Voila, single-input clock exiting the BUFG module.

 

Thanks again, and I hope that helps someone else!

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Scholar
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Registered: ‎02-27-2008
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Visitor
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Registered: ‎08-15-2013

I can't thank you enough for your help, Austin.

 

So that no one else has to spend the time I did scouring the internet for this information, I figure I'll post my solution for anyone else who wants to turn the differential clock into a single-input clock (without changing the frequency).

 

In the UCF file:

 

NET "CLK_P" LOC = "R3" | IOSTANDARD = "DIFF_SSTL15";

NET "CLK_N" LOC = "P3" | IOSTANDARD = "DIFF_SSTL15";

 

Then in my schematic file, I wired CLK_P and CLK_N into an IBUFGDS module, and then wired that into a BUFG module.

 

Voila, single-input clock exiting the BUFG module.

 

Thanks again, and I hope that helps someone else!

View solution in original post

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