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12,079 Views
Registered: ‎05-07-2012

ADC Interface for spartan 6 FPGA

Hi,

im trying to interface 4 channel LVDS o/p , 16 bit DDR ADC interface with FPGA.  Currently im facing the timing issues to get the serial data. Here not used the ISERDES. ISERDES can make better timing solutions??? how to align the bit clock ???

 

Can you please suggest hoe to do that..

 

 

Thanks

Raj 

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Scholar
Scholar
12,075 Views
Registered: ‎02-27-2008

Re: ADC Interface for spartan 6 FPGA

Raj,


First, I would look at the A/D manufacturers website, and see what they already have.  They may have a free IP core already written.  Next I would ask the field applications engineer for the same thing at that company, or its distributor.


If both of those don't suceed, then I would look for something online.  If that doesn't work, I would look for anything similar.  Is the A/D also made by another company (second source, or perhaps primary source)?

 

Generally, if it is useful, it has already been done.


If you need help or support on use of the ISERDES, there is a lot of documentation, and applications notes, with reference designs.

 

Just Google:  iserdes applications note

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎02-25-2008

Re: ADC Interface for spartan 6 FPGA


@austin wrote:

Raj,


First, I would look at the A/D manufacturers website, and see what they already have.  They may have a free IP core already written. 


 

If only! I've asked the Analog Devices and Linear Technology support staff if they already had, or could provide, bus-functional models of their parts. LT simply ignored the request, and the Analog Devices support guy sent me an IBIS model! A back-and-forth with the AD support guy was pointless, as I tried to explain why I wanted a BFM model, and he simply didn't get it. I did tell our local FAEs for both companies that they should provide those models, both FAEs understood why I thought this was important and said they'd take it up the chain of command, but convincing the corporations that such models are in their best interest seems like a long shot.

 

Of course, if you look at the digital interfaces on many ADCs, you wonder what the heck they were thinking when they implemented them! Bizarre is the word I use to describe some of them.

 

So asking for a "core" for the FPGA side is likely a dead end. I can do the interface, but I'd like to prove it against a vendor-supplied model, and that's the point the vendors don't get.

 


If both of those don't suceed, then I would look for something online.  If that doesn't work, I would look for anything similar.  Is the A/D also made by another company (second source, or perhaps primary source)?


 

Leading-edge high-speed ADCs tend to be completely sole-sourced.

----------------------------Yes, I do this for a living.
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Registered: ‎05-07-2012

Re: ADC Interface for spartan 6 FPGA

Thanks... Im using the TI ADS6444 in my design. I have designed the deserialiser without bit clock alighment and ISERDES. It gives the timing problem. But i try to do with lower freq, its working fine... but for high freq it doesnt work

 

FCLK = 100MHz

BitCLK = 400MHZ

DDR, 16 bit serialization

 

 

Please suggest the method to implement..

 

Thanks again

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Scholar
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Registered: ‎02-27-2008

Re: ADC Interface for spartan 6 FPGA

At the higher frequencies,


You will need to use a dynamic loop to track the timing, and find hte center of the eye, or proper time to sample.

 

http://www.xilinx.com/support/documentation/application_notes/xapp866.pdf

 

http://www.xilinx.com/support/documentation/application_notes/xapp860.pdf

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎05-07-2012

Re: ADC Interface for spartan 6 FPGA

Thanks for the reply... Any reference or application notes for spartan 6 fpga??? since the ISERDES is different instants with comapared to virtex 4/5...

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Instructor
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Registered: ‎07-21-2009

Re: ADC Interface for spartan 6 FPGA

Raj,

 

There is much useful material to be found in XAPP495, for implementing dynamicaly centred serial data inputs.  This is written for a completely different application, but the general problems to be solved (and the solutions) are much more alike than they are different from your application.

 

You should also study UG381, particularly the IDELAY2 and ISERDES2 functions described in the Advanced SelectIO Logic Resources section.  Unfortunately, there are some missing and misleading diagrams in this section, but you will learn quite a bit.

 

You can also learn quite a bit with some user forum searches.  I have posted in these forums several rants about the UG381 document shortcomings (which will likely never be corrected), and there have been numerous threads discussing the care and feeding of IDELAY2 and ISERDES2 blocks.

 

-- Bob Elkind

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Registered: ‎03-08-2012

Re: ADC Interface for spartan 6 FPGA

Hi,
im trying to interface ad7865 ADC with spartan3an FPGA. With respect to the timing signals of ad7865 i need to design a vhdl code. can anyone please help me.
thanking u.
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Registered: ‎03-08-2012

Re: ADC Interface for spartan 6 FPGA

Hi,
im trying to interface ad7865 ADC with spartan3an FPGA. With respect to the timing signals of ad7865 i need to design a vhdl code. can anyone please help me.
thanking u.

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Instructor
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Registered: ‎07-21-2009

krnth31: please start a new thread

krnth31,

 

It is considered extremely rude and disrespectful to post with an unrelated question or topic to an existing thread.  This thread is for discussing raj's design, not yours.

 

Please start a new thread to discuss your design.

 

-- Bob Elkind

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2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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Re: ADC Interface for spartan 6 FPGA

Thanks for inputs... I did the coding without ISERDES and adjusted bit clock.

 

I got the output at post-route simulation but in the HW i cant get it. In the HW i get it for one channel...

 

 

Any suggestions to overcome this??  Thanks again for ur help 

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Re: ADC Interface for spartan 6 FPGA


@kpalanivelraj wrote:

Thanks for inputs... I did the coding without ISERDES and adjusted bit clock.

 

I got the output at post-route simulation but in the HW i cant get it. In the HW i get it for one channel...

 

 

Any suggestions to overcome this??  Thanks again for ur help 


Pull out your oscilloscope and look at the ADC's data and clock outputs at the FPGA pins. See what the delay is between them. The idea is to put the clock edge in the center of the bit time, which you can do with a variety of mechanisms in the FPGA.

 

Of course you have a problem if that clock-to-out varies significantly from part to part ...

----------------------------Yes, I do this for a living.
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Re: ADC Interface for spartan 6 FPGA

I got the output at post-route simulation but in the HW i cant get it. In the HW i get it for one channel...

 

With multiple data channels, and a 800Mb/sec data rate (per channel), the odds of success with a simple data+clock scheme are quite low.  A delay to position the input clock perfectly for one input data channel is unlikely to provide adequate timing margins for the other data channels.  Independent clock <--> data timing adjustments will provide better timing margins, and dynamic timing calibrations will provide even better timing margins (and better reliability).  In other words, consider using the Spartan-6 IDELAY2 blocks in DIFF_PHASE_DETECTOR mode.

 

The reason I referred you to the XAPP495 example is this:  HDMI does not presume any channel-to-channel or data-to-clock timing alignment.  The same solutions effective for HDMI input should be equally effective for your application.

 

This thread may be interesting to you.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Re: ADC Interface for spartan 6 FPGA

thanks

 

this is teh lvds to single convertion


-- VHDL Standard Library

 

library IEEE;
use IEEE.std_logic_1164.all;

-- Device Primitive Library
Library UNISIM;
use UNISIM.vcomponents.all;

------------------------------------------------------------------------------------------
-- Entity Name : LVDS_BLOCK
-- I/O Port declarations
entity LVDS_BLOCK is
port (
-- Channel 0 - LSB LVDS input
DA0_P : in std_logic;
DA0_M : in std_logic;

-- Channel 0 - MSB LVDS input
DA1_P : in std_logic;
DA1_M : in std_logic;

-- Channel 1 - LSB LVDS input
DB0_P : in std_logic;
DB0_M : in std_logic;

-- Channel 1 - MSB LVDS input
DB1_P : in std_logic;
DB1_M : in std_logic;

-- Channel 2 - LSB LVDS input
DC0_P : in std_logic;
DC0_M : in std_logic;

-- Channel 2 - MSB LVDS input
DC1_P : in std_logic;
DC1_M : in std_logic;

-- Channel 3 - LSB LVDS input
DD0_P : in std_logic;
DD0_M : in std_logic;

-- Channel 3 - MSB LVDS input
DD1_P : in std_logic;
DD1_M : in std_logic;

-- Data Clock (350MHz) LVDS input
DCLK_P : in std_logic;
DCLK_M : in std_logic;

-- Frame Clock (50MHz) LVDS input
FCLK_P : in std_logic;
FCLK_M : in std_logic;

-- Channel 0 LSB serial output
DA0 : out std_logic;
-- Channel 0 MSB serial output
DA1 : out std_logic;
-- Channel 1 LSB serial output
DB0 : out std_logic;
-- Channel 1 MSB serial output
DB1 : out std_logic;
-- Channel 2 LSB serial output
DC0 : out std_logic;
-- Channel 2 MSB serial output
DC1 : out std_logic;
-- Channel 3 LSB serial output
DD0 : out std_logic;
-- Channel 3 MSB serial output
DD1 : out std_logic;

-- Data Clock (350MHz) output
DCLK : out std_logic;

-- Frame Clock (50MHz) output
FCLK : out std_logic);
end LVDS_BLOCK;

architecture STRUCTURAL of LVDS_BLOCK is
begin
------------------------------------------------------------------------------------------
-- Data Clock LVDS (350 MHz)
-- Differential Signaling Dedicated Input Clock Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
DCLK_LVDS : IBUFGDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFGDS primitive
port map (
O => DCLK, -- Data Clock - 1 bit serial output
I => DCLK_P, -- Data Clock Diff_p buffer input
IB => DCLK_M); -- Data Clock Diff_n buffer input

------------------------------------------------------------------------------------------
-- Frame Clock LVDS (50 MHz)
-- Differential Signaling Dedicated Input Clock Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
FCLK_LVDS : IBUFGDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFGDS primitive
port map (
O => FCLK, -- Frame Clock - 1 bit serial output
I => FCLK_P, -- Frame Clock Diff_p buffer input
IB => FCLK_M); -- Frame Clock Diff_n buffer input


------------------------------------------------------------------------------------------
-- Channel 0 LSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH0_LSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DA0, -- Channel 0 LSB serial output
I => DA0_P, -- Channel 0 LSB Diff_p buffer input
IB => DA0_M ); -- Channel 0 LSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 0 MSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH0_MSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DA1, -- Channel 0 MSB serial output
I => DA1_P, -- Channel 0 MSB Diff_p buffer input
IB => DA1_M ); -- Channel 0 MSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 1 LSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH1_LSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DB0, -- Channel 1 LSB serial output
I => DB0_P, -- Channel 1 LSB Diff_p buffer input
IB => DB0_M ); -- Channel 1 LSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 1 MSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH1_MSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DB1, -- Channel 0 MSB serial output
I => DB1_P, -- Channel 0 MSB Diff_p buffer input
IB => DB1_M ); -- Channel 0 MSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 2 LSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH2_LSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DC0, -- Channel 2 LSB serial output
I => DC0_P, -- Channel 2 LSB Diff_p buffer input
IB => DC0_M ); -- Channel 2 LSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 2 MSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH2_MSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DC1, -- Channel 2 MSB serial output
I => DC1_P, -- Channel 2 MSB Diff_p buffer input
IB => DC1_M ); -- Channel 2 MSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 3 LSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH3_LSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DD0, -- Channel 3 LSB serial output
I => DD0_P, -- Channel 3 LSB Diff_p buffer input
IB => DD0_M ); -- Channel 3 LSB Diff_n buffer input

------------------------------------------------------------------------------------------
-- Channel 3 MSB Data LVDS
-- Differential Signaling Input Buffer
-- LVDS to 1 bit
-- converts the differential voltage signal to 1 bit serial data
CH3_MSB_LVDS : IBUFDS
-- General Declaration for IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
-- I/O port of IBUFDS primitive
port map (
O => DD1, -- Channel 3 MSB serial output
I => DD1_P, -- Channel 3 MSB Diff_p buffer input
IB => DD1_M ); -- Channel 3 MSB Diff_n buffer input


end STRUCTURAL;

 ------------------------------------------------------------------------------------------

SERDES  modules is


----------------------------------------------------------------------------------------------------
-- VHDL Standard Libirary
library IEEE;
use IEEE.std_logic_1164.ALL;

-- Device Primitive Library
Library UNISIM;
use UNISIM.vcomponents.all;

------------------------------------------------------------------------------------------
-- Entity Name : LVDS Block
-- I/O Port declarations
entity SERDES_BLOCK is
generic (
-- ADC resolution - 14 bit data
DATA_WIDTH :integer := 16);
port (
-- Active Low Asynchronous Reset
RSTn : in std_logic;

-- 700 MHz DDR data sampling clock
CLK_DATA : in std_logic;

-- Frame Clock
CLK_FRAME : in std_logic;

-- 1 bit serial LSB data for channel
LSBDATA_IN : in std_logic;

-- 1 bit serial MSB data for channel
MSBDATA_IN : in std_logic;

-- 14 bit parallel data output
DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0));

end SERDES_BLOCK;

architecture BEHAVIORAL of SERDES_BLOCK is

-- Internal Signals for LSB and MSB data

-- Constant for LSB data width
constant LSB_MSB_DATA_WIDTH: integer :=4;

-- 7 bit LSB and MSB internal signal
signal DATA_LSB_P,DATA_LSB_N : std_logic_vector(LSB_MSB_DATA_WIDTH-1 downto 0);
signal DATA_MSB_P,DATA_MSB_N : std_logic_vector(LSB_MSB_DATA_WIDTH-1 downto 0);

signal DATA_MSB,DATA_LSB : std_logic_vector (7 downto 0);


begin


------------------------------------------------------------------------------------------
-- Process : LSB data Shift Register (7 bit)
-- Clock : Data sampling clock 700 MHz
-- Reset : RSTn Asynchronous active low reset
-- Description : Conveting the single bit LSB data to 7 bit parallel data
-- Data Format : Little Endian (LSB First)
process (CLK_DATA, RSTn)
begin
-- Asynchronous active low reset
if RSTn='1' then
DATA_LSB_P <= "0000";
-- 350 MHz DDR data sampling at 700MHz
elsif rising_edge(CLK_DATA) then
--DATA_LSB <= LSBDATA_IN & DATA_LSB( LSB_MSB_DATA_WIDTH-1 downto 1);
DATA_LSB_P <= DATA_LSB_P( 2 downto 0) & LSBDATA_IN ;
end if;
end process;



process (CLK_DATA, RSTn)
begin
-- Asynchronous active low reset
if RSTn='1' then
DATA_LSB_N <= "0000";
-- 350 MHz DDR data sampling at 700MHz
elsif falling_edge(CLK_DATA) then
--DATA_LSB <= LSBDATA_IN & DATA_LSB( LSB_MSB_DATA_WIDTH-1 downto 1);
DATA_LSB_N <= DATA_LSB_N(2 downto 0) & LSBDATA_IN ;
end if;
end process;

------------------------------------------------------------------------------------------
-- Process : MSB data Shift Register (7 bit)
-- Clock : Data sampling clock 700 MHz
-- Reset : RSTn Asynchronous active low reset
-- Description : Conveting the single bit MSB data to 7 bit parallel data
-- Data Format : Little Endian (LSB First)
process (CLK_DATA, RSTn)
begin
-- Asynchronous active low reset
if RSTn='1' then
DATA_MSB_P <= "0000";
-- 350 MHz DDR data sampling at 700MHz
elsif rising_edge(CLK_DATA) then
--DATA_MSB <= MSBDATA_IN & DATA_MSB( LSB_MSB_DATA_WIDTH-1 downto 1) ;
DATA_MSB_P <= DATA_MSB_P(2 downto 0) & MSBDATA_IN;

end if;
end process;


process (CLK_DATA, RSTn)
begin
-- Asynchronous active low reset
if RSTn='1' then
DATA_MSB_N <= "0000";
-- 350 MHz DDR data sampling at 700MHz
elsif falling_edge(CLK_DATA) then
--DATA_MSB <= MSBDATA_IN & DATA_MSB( LSB_MSB_DATA_WIDTH-1 downto 1) ;
DATA_MSB_N <= DATA_MSB_N(2 downto 0) & MSBDATA_IN;

end if;
end process;

------------------------------------------------------------------------------------------
-- Process : Framing the LSB and MSB data
-- Clock : Frame clock 50 MHz
-- Reset : RSTn Asynchronous active low reset
-- Description : Concatenate the LSB and MSB data on rising edge of the frame clock
-- Data Format : Little Endian (LSB First)
process (CLK_FRAME, RSTn)
begin
-- Asynchronous active low reset
if RSTn='1' then
DATA_OUT <= "0000000000000000";
elsif rising_edge (CLK_FRAME) then
DATA_OUT <= DATA_MSB_P(3) & DATA_MSB_N(3) & DATA_MSB_P(2) & DATA_MSB_N(2)& DATA_MSB_P(1) & DATA_MSB_N(1) & DATA_MSB_P(0) & DATA_MSB_N(0)& DATA_LSB_P(3) & DATA_LSB_N(3) & DATA_LSB_P(2) & DATA_LSB_N(2)& DATA_LSB_P(1) & DATA_LSB_N(1) & DATA_LSB_P(0) & DATA_LSB_N(0) ;
end if;
end process;



end BEHAVIORAL;

 

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Registered: ‎05-07-2012

Re: ADC Interface for spartan 6 FPGA

Dear Bo,

 

i could not able to understand the bit clock alignment.  Is there any documents to describe the bit clock and data alignment for ADC interface in FPGA.

 

 

Thanks a lot for ur help..

 

-Raj

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Registered: ‎07-21-2009

Re: ADC Interface for spartan 6 FPGA

i could not able to understand the bit clock alignment.  Is there any documents to describe the bit clock and data alignment for ADC interface in FPGA.

 

Bit clock to data alignment is a general design problem, and is not specific to using an ADC.

 

How are you aligning the input data and the data sampling clock to one another?  There are many ways to do this.  I tried to describe the differences between several approaches in the linked thread.  If you read this thread, can you ask more specific questions in the context of the descriptions?

 

Have you read the UG381 sections describing the IODELAY2 blocks and operating modes?  UG381 does a very good job of describing bit clock and data alignment.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
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Re: ADC Interface for spartan 6 FPGA

It looks like the top level of your code is missing from your post.  For example, where is the logic which generates CLK_DATA?  I am not a VHDL expert, so forgive me if I am mistaken out of ignorance.

 

-- Bob Elkind

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Summary:
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3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
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Re: ADC Interface for spartan 6 FPGA

Dear Bob,

 

CLK_DATA is from the LVDS module. Here im not using the any logic for bit clock. Simply take it from IBUFGDS block and used for deserialization.

 

Thanks for ur reply. I will study the ug381 for IODELAY and reply back to you.

 

-Raj

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Re: ADC Interface for spartan 6 FPGA

CLK_DATA is from the LVDS module. Here im not using the any logic for bit clock. Simply take it from IBUFGDS block and used for deserialization.

 

1.  IBUFGDS is not a clock buffer.  It is an ordinary input buffer located at a GCLK pin.  You need a clock buffer, either BUFG or BUFIO2 or BUFPLL.

 

2.  Either I do not understand VHDL syntax well enough, or my eyesight is bad.  In your code I could not see a source for the clock signal CLK_DATA.

 

-- Bob Elkind

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Registered: ‎05-07-2012

Re: ADC Interface for spartan 6 FPGA

Hi BOB,

 

Im using the application note xapp 1064 reference design (DDR receiver) for this application.IODELAY and ISERDES modules are used for DDR reception.

 

In that design, the strobe signal to ISERDES is generated by BUFIO2 module. This is based on the data clock module.

 

But for the ADC interface,  the strobe will be based on the frame clock.

 

Please let me how to generate the strobe to ISERDES 2 based on the frame clock.

 

Thanks

raj

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