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Visitor grinaldi
Visitor
6,027 Views
Registered: ‎10-28-2015

AXI Crossbar SAMD simulation issue

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Hi,

 

I'm using the axi_crossbar IP with 3 masters and 9 slaves (or 3 slaves and 9 master ports on the axi_crossbar).

 

When I run SASD, my simulation runs fine.

 

When I configure and run SAMD, my simulation fails because I see that for a read back data the RVALID gets output from the axi_crossbar to two masters.  I think only one RVALID should be output back to the proper master.

Maybe the ID setting is not correct.

 

Does anyone have the a working simulation parameter settings for the axi_crossbar SAMD verilog generated file?

 

I think my settings may be incorrect and want to compare.

 

Thanks

 

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Xilinx Employee
Xilinx Employee
11,237 Views
Registered: ‎08-02-2011

Re: AXI Crossbar SAMD simulation issue

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Hello,

 

It looks like you are driving all the ID bits. The crossbar uses a subset of the ID bits for routing information (I can't remember offhand if it's the upper bits or lower bits) so you shouldn't drive those bits. The specifics of that should be in the PG, but I remember seeing something similar a long time ago when driving the wrong ID bits.

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Xilinx Employee
Xilinx Employee
6,024 Views
Registered: ‎08-02-2011

Re: AXI Crossbar SAMD simulation issue

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Hello,

 

Can you show a screenshot of what you're seeing?

Are you looking at the right rvalid bits for the given slave?

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Visitor grinaldi
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Registered: ‎10-28-2015

Re: AXI Crossbar SAMD simulation issue

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Hi,

 

I'm adding the simulation jpeg. See attachment.

You can see there is read address to 00000500 and S_AXI_ARREADY = 2 hex and S_AXI_ARVALID= 2 hex (which means SLOT1 master is active).

So I'm expecting S_AXI_RVALID = 2 hex

Instead I'm seeing S_AXI_RVALID = 3 hex at time around 4970ns which is unexpected and causes data corruption problems.

 

Below are the PARAMETER settings for axi_crossbar_v2_1_axi_crossbar.v

I'm instantiating the axi_crossbar_v2_1_axi_crossbar module.

 

Thanks for reviewing this post.

 

 

module axi_crossbar # (parameter

                                  ID_BITS = 5,
                                  ADDR_BITS = 32,
                                  DATA_BITS = 128,
                                  USER_BITS = 1,
                                  N_SLV = 3,

axi_crossbar_v2_1_axi_crossbar #(
                                  .C_FAMILY("rtl"),
                                  .C_NUM_SLAVE_SLOTS(N_SLV),
                                  .C_NUM_MASTER_SLOTS(N_MST),
                                  .C_AXI_ID_WIDTH(ID_BITS),
                                  .C_AXI_ADDR_WIDTH(ADDR_BITS),
                                  .C_AXI_DATA_WIDTH(DATA_BITS),
                                  .C_AXI_PROTOCOL(0),
                                  .C_NUM_ADDR_RANGES(1),
      .C_M_AXI_BASE_ADDR(576'h00000000_fffff000_00000000_80080000__00000000_80040000__00000000_80002000__00000000_80001000__00000000_80000000__00000000_10000000__00000000_00100000__00000000_00000000), // 9*16 = 144*4 = 576 bits
                                            // Base address of each range of each MI slot.
                                  .C_M_AXI_ADDR_WIDTH(288'h0000000c_0000000d_00000012_0000000c_0000000c_0000000c_00000013_00000012_0000000d), // C_M_AXI_ADDR_BITS  6*8=48 *4 = 192 bits
                                            // Number of low-order address bits that are used to select locations within each address range of each MI slot.
                                  .C_S_AXI_BASE_ID(96'h00000000_00000000_00000000), // was 0 0 0
                                  .C_S_AXI_THREAD_ID_WIDTH(96'h00000005_00000005_00000005), // C_S_AXI_THREAD_ID_BITS
                                  .C_AXI_SUPPORTS_USER_SIGNALS(1),

                                  .C_AXI_AWUSER_WIDTH(USER_BITS), // C_AXI_AWUSER_BITS
                                  .C_AXI_ARUSER_WIDTH(USER_BITS), // C_AXI_ARUSER_BITS
                                  .C_AXI_WUSER_WIDTH(USER_BITS), // C_AXI_WUSER_BITS
                                  .C_AXI_RUSER_WIDTH(USER_BITS), // C_AXI_RUSER_BITS
                                  .C_AXI_BUSER_WIDTH(USER_BITS), // C_AXI_BUSER_BITS
                                  .C_M_AXI_WRITE_CONNECTIVITY(288'h00000007_00000007_00000007_00000007_00000007_00000007_00000007_00000007_00000007), // was 7 7 7 7 7 7 7 7 7
                                  .C_M_AXI_READ_CONNECTIVITY(288'h00000007_00000007_00000007_00000007_00000007_00000007_00000007_00000007_00000007),
                                  .C_R_REGISTER(0),
                                  .C_S_AXI_SINGLE_THREAD(96'h00000001_00000001_00000001),
                                                      // 0 = Implement separate command queues per ID thread.
                                                      // 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
                                  .C_S_AXI_WRITE_ACCEPTANCE(96'h00000001_00000001_00000001),
                                                      // Maximum number of active write transactions that each SI
                                                      // slot can accept. (Valid only for SAMD)
                                  .C_S_AXI_READ_ACCEPTANCE(96'h00000001_00000001_00000001),
                                                      // Maximum number of active read transactions that each SI
                                                      // slot can accept. (Valid only for SAMD)
                                  .C_M_AXI_WRITE_ISSUING(288'h00000001_00000001_00000001_00000001_00000001_00000001_00000001_00000001_00000001),
                                                      // Maximum number of data-active write transactions that
                                                      // each MI slot can generate at any one time. (Valid only for SAMD)
                                  .C_M_AXI_READ_ISSUING(288'h00000001_00000001_00000001_00000001_00000001_00000001_00000001_00000001_00000001),
                                                      // Maximum number of active read transactions that
                                                      // each MI slot can generate at any one time. (Valid only for SAMD)
                                  .C_S_AXI_ARB_PRIORITY(96'h00000000_00000000_00000000), //3*32=96

                                                      // Arbitration priority among each SI slot.
                                                      // Higher values indicate higher priority.
                                                      // 0 0 0 = round robin priority
                                 .C_M_AXI_SECURE(288'h00000001_00000001_00000001_00000001_00000001_00000001_00000001_00000001_00000001), // 9*32=288
                                                      // Indicates whether each MI slot connects to a secure slave
                                                      // (allows only TrustZone secure access).
                                  .C_CONNECTIVITY_MODE(1)
                                                      // 0 = Shared-Address Shared-Data (SASD).
                                                      // 1 = Shared-Address Multi-Data (SAMD).
                                 )
        axi_crossbar_v2_1
        (
          .aclk                             (aclk),
          .aresetn                          (aresetn),

 

 

 

 

samd_s_axi_rvalid_3_to_xilinx.jpg
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Visitor grinaldi
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6,008 Views
Registered: ‎10-28-2015

Re: AXI Crossbar SAMD simulation issue

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Add one missed parameter

 

                                  N_MST = 9,

 

for this setting

 

                                  .C_NUM_MASTER_SLOTS(N_MST),

 

 

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Visitor grinaldi
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5,863 Views
Registered: ‎10-28-2015

Re: AXI Crossbar SAMD simulation issue

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Is anyone from xilinx monitoring this posting?

 

It seems like for SAMD configuration, the axi_crossbar for a MASTER read to a SLAVE (peripheral),

issues RVALID for ALL MASTERS.

Please confirm this observation.

 

Also, if my observation from above is correct, how does the master know if the RDATA,RVALID from axi_crossbar

is issued by the MASTER and thus accept it.

 

Lastly, if for two MASTERS (one MASTER issues RD, and second MASTER issues WR to the same SLAVE)

about the same time for SAMD,

how does axi_crossbar manage the coordination of these two operations?

Does it give priority of WR over RD and does it allow this operation to complete before issuing the RD operation?

Are there any configuration settings to handle this almost simultaneous operation to same SLAVE (peripheral)?

 

 

 

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Xilinx Employee
Xilinx Employee
11,238 Views
Registered: ‎08-02-2011

Re: AXI Crossbar SAMD simulation issue

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Hello,

 

It looks like you are driving all the ID bits. The crossbar uses a subset of the ID bits for routing information (I can't remember offhand if it's the upper bits or lower bits) so you shouldn't drive those bits. The specifics of that should be in the PG, but I remember seeing something similar a long time ago when driving the wrong ID bits.

www.xilinx.com
Visitor grinaldi
Visitor
5,667 Views
Registered: ‎10-28-2015

Re: AXI Crossbar SAMD simulation issue

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Thanks,

 

that make sense. I am still struggeling with the SAMD configuration of the axi crossbar.

Do you have any example/tutorial available? I couldn't find anything on the xilinx website.

 

Thanks,

Giacomo

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