01-18-2017 08:49 PM - edited 01-18-2017 08:50 PM
I am using AXI interconnect RTL to connect 1 slave device to 2 Masters. following is the spec of the IP
Address width of master, slave0, slave1 : 32
Data width of master, slave1 : 64
Data width of slave0 : 32.
A read cycle is initiated to Slave1 port. Arvalid is asserted at master output and Arready is also obtained at master's input from the actual slave.
However, Rvalid from slave is not obtained at Slave0 port's Rvalid. I have added waveform snapshot of the scenario.
Please suggest what could be the issue.
01-19-2017 12:03 AM
Did you check the address of the slave?
01-19-2017 11:17 AM - edited 01-19-2017 11:22 AM
ARID is a good candidate to look at if your master (connected the the AXI_IC slave) has a thread_id >1.
If not, then there's no ID width routing done (i.e. ID_WIDTH would be zero). Good to verify anyway,
but I'm not sure this is the problem.
I don't think addressing is a problem as the Interconnect is routing the read request through correctly to the final slaves. It's the return rdata, that doesn't appear to be propogating back through to the master.
I'd ask more questions too:
For the Masters and Slaves - your IP or Xilinx or ???
Full AXI4, or AXI-Lite?
What version of the Xilinx AXI_INTERCONNECT (1.7, or 2.1)
Timing closed - what speeds are you operating at? Are all ports synchronous?
Do any transfers work? Or are you showing the first (and only) unworking xfer?
Other "duh" things to looks at - is everything out of reset? Clocks stable?