08-17-2016 03:23 PM
I am using the AXI stream FIFO to stream data into the Rx side and eventually will be read back from the processor through AXI bus as well. There are some configuration with the AXI stream FIFO need to be configure. How can I read back the FIFO content?
Do I read base_address + 0x1C and FIFO data will be read out at base_address + 0x20?
Is the FIFO data will be update to the base_address + 0x20 on every read till it is empty?
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