how can I configure the delay/gap between two data transfer. The AXI clock is 100 Mhz and it is divided by 2 for AXI quad SPI block. I would liek to transfer the 8 bit data at 20ns of clock and gap of 20ns bwteen two transfer.
You cannot control the timing like that with AXI SPI. You would need to create a custom controller in programmable logic.
I don't think that requiring a delay between bytes is compliant to the SPI specification. That timing diagram doesn't have a specific name for that delay, are you sure it is required to exist, let alone be 20ns? It may just be drawn like that to show gaps are allowed between bytes for SPI controller that don't have a buffer.
Depending on what that delay is relative to you might be able to run the clock at 25MHz and get a 20ns low period between rising edges of a continuous data stream.