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Voyager
Voyager
1,894 Views
Registered: ‎10-31-2016

AXI quad SPI

hi, 

 

I like to have delay between two SPI data transfer 

 

When I try the below code there is no delay between two data (8 bit) transfer

XSpi_Transfer(SpiInstancePtr,  WriteBuffer, NULL, 17); 

 

on the other hand when I try the below code then there is huge delay

XSpi_Transfer(SpiInstancePtr, right_reg_0, NULL, 1);
XSpi_Transfer(SpiInstancePtr, right_reg_1, NULL, 1)

 

 

how can I configure the delay/gap between two data transfer. The AXI clock is 100 Mhz and it is divided by 2 for AXI quad SPI block. I would liek to transfer the 8 bit data at 20ns of clock and gap of 20ns bwteen two transfer. 

 

Please let me know how can I proceed ?

 

Capture.PNG

 

thank you 

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Explorer
Explorer
1,879 Views
Registered: ‎03-31-2016

You cannot control the timing like that with AXI SPI.  You would need to create a custom controller in programmable logic.

 

I don't think that requiring a delay between bytes is compliant to the SPI specification.  That timing diagram doesn't have a specific name for that delay, are you sure it is required to exist, let alone be 20ns?  It may just be drawn like that to show gaps are allowed between bytes for SPI controller that don't have a buffer.

 

Depending on what that delay is relative to you might be able to run the clock at 25MHz and get a 20ns low period between rising edges of a continuous data stream.

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