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Contributor
Contributor
1,802 Views
Registered: ‎11-07-2016

Analysis window

Is there a way to open an analysis window with the real cycles of the project instead the estimate cycles of synthesis..??

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Advisor
Advisor
1,782 Views
Registered: ‎04-26-2015

No. To do that, HLS would need to insert a debug core to trace every signal inside the block at runtime, which would take far more resources than the FPGA had available.

 

Apart from things outside of HLS's control (eg. congestion on the AXI buses, stream masters or slaves not being ready) the analysis displayed after synthesis should be correct. Are you seeing major differences?

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Contributor
Contributor
1,736 Views
Registered: ‎11-07-2016

Yes, at least two million cycles.

 

Synthesis export ~3500000 cycles for the whole project and cosim export ~1600000 cycles.

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