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Visitor tinus
Registered: ‎05-10-2017

Aurora 8b10b dual lane not working

Hello! I am using Vivado 2016.3 and LogiCORE IP Aurora 8B/10B v11.0 to communicate between 2 boards with the following settings: 


Lane Width: 2;

Number of lanes: 2;

Line Rate: 4.000 Gbps;

GT ref clock: 200MHz;

INIT clock: 200MHz;

Dataflow mode: Duplex;

Interface: streaming;


Fpga1: kintex7 xc7k160tfbg676 -1

Lane assignment: Lane1 (X0Y4), Lane2 (X0Y2)

Board2: Guido

Fpga2: kintex7 xc7k160tffg676 -2

Lane assignment: Lane1 (X0Y4), Lane2 (X0Y5)


Aurora 8b10b near-end PCS and PMA loopback tests work properly for both FPGAs while far-end PCS and PMA tests show a lot of soft errors that cause hard errors and so channel failure.


I have tested the status link of the 2 lanes with IBERT 7 series GTX (3.0) and Serial analyzer at 4.000 Gbps and there were no errors in all loopback tests and in normal operation with 32 bit PRBS7 data pattern and the same clocks of Aurora8b10b. I made the eye diagram for both FPGAs and swept between TX-pre cursor, TX-post cursor, TX diff swing parameters to find the optimum eye. I chose

TX pre-cursor: 1,67 dB

TX post-cursor: 0.68 dB

TX diff swing: 1018 mV

With these values, I obtained very similar eye scan for all receivers (see attachment).


In aurora 8b10b, when creating the core, I have checked the additional transceivers and status port option and I have put the aforementioned optimum values for TX pre-cursor, TX post-cursor, TX diff swing. In near-end PCS and PMA tests there are no errors as before. Unfortunately, far-end PCS and PMA loopback tests still show hard errors because of soft errors and rx_buf_err_out which goes high (rx buffer of FPGA1 underflows and rx buffer of FPGA2 overflows) causing channel failure. I have changed the values of CLK_MIN_LAT to 1 and CLK_MAX_LAT to 60 but anything has changed.

I diminished the line rate at 0.600 Gbps and the system works properly in all loopback tests and normal operation. At 4.000 Gbps the system works properly when I use single lanes (I have checked both lanes separately). These problems arise when I use the 2 lanes togethers at high line rates. What can be wrong?