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vinod_1987
Observer
Observer
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Registered: ‎08-17-2015

Aurora design example: #CDC file

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Hello,

        I'm using Aurora 8b/10b ip core on virtex 5 fpga, while creating *.CDC file, in select net window, i could see only top module. All other submodules are hidden. please find it in attachment 1.

 

when i run chipscope, (i tapped frame generator, Data), it showing only one generated data. what is the issue. please find it in attachment 2.

 

thank you.

 

 

Attachment-1.png
attachment-2.png
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venkata
Moderator
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7,341 Views
Registered: ‎02-16-2010
Looks like the design hierarchy is flattened. I see the scroll bar is fairly long with several signals.

Check if setting keep_hierarchy attribute to "TRUE" can help for your purpose.
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venkata
Moderator
Moderator
7,342 Views
Registered: ‎02-16-2010
Looks like the design hierarchy is flattened. I see the scroll bar is fairly long with several signals.

Check if setting keep_hierarchy attribute to "TRUE" can help for your purpose.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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vinod_1987
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Registered: ‎08-17-2015

Thank you. 

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