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atofe
Newbie
Newbie
1,286 Views
Registered: ‎12-26-2014

Bidir (inout) bus problem

Hi!

 

I want to make a simple PCI card to control stepper motor drivers, but for now, I wanted to start with something less complicated than PCI, so I wrote this module. creg [3:0] is a set of registers that can (should) be readable and writable from the dbus[7:0]. iowr causes dbus contents to be written to register selected by sel[1:0] on the raising edge of dclk. iord should read selected register to dbus, but it doesn't work :-( Of course I want my IC to stop driving the dbus (go to 8'hz) when clock goes low. m13 and m36 are example outputs that would drive other ics on my card (for example STEP/DIR signals for stepper drivers).

 

Module code:

 -------------------------------------------- 

 

 `timescale 1ns / 1ps

module ftest1
(
    input dclk,
    input [1:0]sel,
    input iowr,
    input iord,
    inout [7:0]dbus,
    output m36,
    output m13
);

reg [7:0]creg [3:0];
wire dbus_drv;
wire [7:0]dbus_out;
wire [7:0]dbus_in;

assign m13=creg[1][3];
assign m36=creg[3][6];

assign dbus_drv=dclk & iord & ~(iowr);
assign dbus=(dbus_drv==1'b1)?dbus_out:8'bz;
assign dbus_in=dbus;

assign dbus_out=creg[sel];

always@(posedge dclk)
begin
    if(iowr) creg[sel]=dbus_in;
end

endmodule

--------------------------------------------

 

What am I doing wrong?

I send my testbed code as attachment.

 

 

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1 Reply
muzaffer
Teacher
Teacher
1,274 Views
Registered: ‎03-31-2012

>> Of course I want my IC to stop driving the dbus (go to 8'hz) when clock goes low.

why? what can you do on the other side in half a clock?
If you remove the clock dependency on the tri-state and only depend on iord to control it, your chances of getting it to work is much higher: enable iord, latch the output on the next clock, disable iord on the next clock.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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