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asrarhashmitud
Observer
Observer
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Registered: ‎07-23-2014

Block RAM simulation problem - Not reading from address 0

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Hello All,

 

I was simulating my design with a true dual port block ram 64bit wide and 16 bit deep.

during simulation I noticed that it is always reading 0 from address 0!.

I have initialized the block RAM with a .coe file and it is reading correct data on all other address. Only on address zero is it messing and producing wron data on output.

 

I am attaching the .coe file for clearing my querry and also a snapshot of simulation. Please see the bottom waveforms of Config RAM

 

Can anyone please tell me what I'm doing wrong here?

 

I am nopt using primitive registers as I want only one clock latency. Also I am not using reset on any of the ports.

 

 

Best Regards

Asrar

ramissue.png
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asrarhashmitud
Observer
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7,613 Views
Registered: ‎07-23-2014

Finally got it working,

 

I added a buffer sort of mux to the write enable signals assigned during different states in my state machine.

so now (as far as i guess) the optimizer does not optimize the top level outputs by driving to some value itself, so the RAM gets a solid 0 or 1 on its write enable inputs. Or may be some other reason behind it but after lotsss of trials and iteration... thats how it got working:

 

so wen_alarm_ram is my output signal to the BRAM it was ditinctly assigned '0' or '1' in my state machine.due to some optimization may be, the simulator was tying it to some such zero that it was not able to respond  to.

 

So hardwriring the signal to '0' (wen_alarm_ram <= '0') was working but that would not suffice because i needed to both read and write. so i used an internal signal (wen_alarm_ram_reg) to assign in the states and drove the actual output on basis of that

 

wen_alarm_ram <= '1' when (wen_alarm_ram_reg = '1') else '0';

and that di the trick for me. Address 0 responding correctly now.

 

Thanks all for helping out.

 

Asrar

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aher
Xilinx Employee
Xilinx Employee
5,795 Views
Registered: ‎07-21-2014

hello,

 

have you instantiated the block RAM from templates?

if Yes, try generating BRAM using IP core and initialize it using same .coe file.

 

thanks

Shreyas

 

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asrarhashmitud
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Registered: ‎07-23-2014

Templates?

 

No, I inserted and customized it from IP Catalog. I assigned this .coe file in the Customization GUI.

USing Vivado 2014.3-

 

 

BR

Asrar

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asrarhashmitud
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Registered: ‎07-23-2014
Hello Shreyas,

Were you able to find anything on this? Its a strange and wierd issue
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aher
Xilinx Employee
Xilinx Employee
5,697 Views
Registered: ‎07-21-2014

Hi,

 

attached is the snapshot of simulation at my end.

you can see one clock cycle latency as i have registered the data from "douta" in to the register "temp".

i can get proper data at address "0000".

 

bram_init.png

 

here are few suggestions:

 

1- try resetting output products of the IP and regenerating it.

2- see if you "ena" signal is "1" ( I couldn't see in the snapshot) when you are trying to read the data from the address "0000"

3- if doesnt work please try to simulate only BRAM part in the code (by disabling every other part of the code) as a debug step. 

 

hope this helps.

 

thanks,

Shreyas

 

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asrarhashmitud
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5,621 Views
Registered: ‎07-23-2014

Hello ShreyaS,

 

Thanks for your reply. I tried to simulate using your prescriptions and it turns out that if I feed the "wea" signal directly with 0 or 1, only then it works. but if I feed the "wea" with anything else (lets say an FSM output that switches between 0 and 1 in different states) then it screws the data at zero address. i tried simulting only the RAM which meant ofcourse that I was hardwiring the "wea" pin to "0" and so it was working. but in actual practice I need to both read and write from the BRAM so want to change the state of "wea" pin.

 

Please look into this. Should I send you my design files?

 

 

 

Best Regards

Asrar

 

 

 

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asrarhashmitud
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7,614 Views
Registered: ‎07-23-2014

Finally got it working,

 

I added a buffer sort of mux to the write enable signals assigned during different states in my state machine.

so now (as far as i guess) the optimizer does not optimize the top level outputs by driving to some value itself, so the RAM gets a solid 0 or 1 on its write enable inputs. Or may be some other reason behind it but after lotsss of trials and iteration... thats how it got working:

 

so wen_alarm_ram is my output signal to the BRAM it was ditinctly assigned '0' or '1' in my state machine.due to some optimization may be, the simulator was tying it to some such zero that it was not able to respond  to.

 

So hardwriring the signal to '0' (wen_alarm_ram <= '0') was working but that would not suffice because i needed to both read and write. so i used an internal signal (wen_alarm_ram_reg) to assign in the states and drove the actual output on basis of that

 

wen_alarm_ram <= '1' when (wen_alarm_ram_reg = '1') else '0';

and that di the trick for me. Address 0 responding correctly now.

 

Thanks all for helping out.

 

Asrar

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