I had used XIlinx Paltform Studio(XPS) to build my project. I used AXI4 protocal with 32 bit data and address width to build my project .
In my design I need to perform several Read/Write operations using my firmware code which is written in System C.
i.e. i need to perform 8 bit, 16 bit and 32 bit Read and Write operations.
During these operations, the width of AWSIZE and ARSIZE must be changed, according to READ/WRITE 8/16/31 bits.
i.e for READ/WRITE 8 bits,the AWSIZE/ARSIZE is b'00
READ/WRITE 16 bits,the AWSIZE/ARSIZE is b'01
READ/WRITE 32 bits,the AWSIZE/ARSIZE is b'10
But in Emulation, The AWSIZE/ARSIZE is always set to b'10 when AXI adress/data width is 32bit.
In AXI Reference document, Xilinx has mentioned about AXI SIZE is b'00 for 1byte, b'01 for 2bytes and b'10 for 4bytes.
Why it is always set to b'10 when AXI width is 32 bit. Please help us to find this issue.