UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor avinash200
Visitor
6,351 Views
Registered: ‎05-29-2015

Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

I am testing the memory interface for DDR3 using the given IP core (MIG 2.3) in Vivado 2014.4 for a VC-709 development board and it has been only 3 weeks since I have been tinkering with it. I have followed UG586 (June 4, 2014) and the VC709 MiG Design Guide. I just wanted to outlay some issues for new users working with Vivado 2014 on Windows 8.1, and to enquire whether Xilinx is working on issues in solving these bugs:

 

1. Vivado launches the 64-bit application by default when we open the .xpr file. For all versions of Vivado for which Windows 8.1 support is offerred (2014.3 onwards, I guess), MiG has issues with the 64-bit version of Vivado. At the 'Pin Selection' step of the IP core wizard, when the 'Read XDC/UCF' is entered, the IP core crashes with the following error:


IP_core_failure_cropped.png

The solution is to use 32-bit Vivado with '-m32' option during application launch and then use it for MiG design. The solution is given in the following link (Re: 2014.1 windows 8.1 MIG IP generator fails to run), so I'm not attaching any log files.

This issue is only there in Windows 8.1. The same procedure on Windows 7 works without a glitch.

 

2. From Vivado 2015.1 onwards, Xilinx is removing the 32-bit option. The same bug exists in Vivado 2015.1 also, which renders it unusable for MiG designs in Windows 8.1.

 

3. Behavioral Simulation of the MiG example design fails for Vivado 2014.4 in 32-bit mode:

Sim_failure_crop.png

It works for the 64-bit mode. So, the MiG has to be created in 32-bit mode and the example design simulated in 64-bit mode. I've attached the compressed log file (simulate.rar) of the same for reference.

 

4. Bitstream generation of the MiG example design fails unless the following line is added to constraints file (example_top.xdc) which is provided with the Mig support file rdf0233-vc709-mig-c-2014-4.zip:

 

set_property BITSTREAM.GENERAL.UNCONSTRAINEDPINS Allow [current_design]

All instructions were followed from the VC-709 MiG Design creation guide (November 2014).

 

 

5. In Pg 42 of the VC709 MiG Design Guide, the LED display driver is shown as being instantiated inside example_top.v. in the VHDL example design (example_top.vhd), the led_display_driver is not instantiated like in the verilog file. When the file is added, it sits separately from the top module:

led_driver_absent.png

 

Kindly tell me if I'm mistaken in any of the above points and whether Xilinx will solve these issues in future releases. Please tell me any more log files are required to address these issues.

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
11,066 Views
Registered: ‎07-11-2011

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Hi,

 

I do not think modified board design files will be provied for VHDL, if you wnat to test the board with VHDL then, go for new project, add MIG IP, and go with verify xdc and update deisgn and pin out pin out option in MIG, then import xdc and prj from the provided zip files.

If you need LED driver then you may need to instantiate it on your own vhdl tpp level file, but it is just needed for extensive testing and is not mandatory. You can use ILA to monitor init_calib_done and error siganls.

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
6 Replies
Xilinx Employee
Xilinx Employee
6,317 Views
Registered: ‎09-20-2012

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Hi,

 

Regarding the issue 1, refer to this article http://www.xilinx.com/support/answers/63393.html

 

This issue is already reported to factory and they are working on it.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Visitor avinash200
Visitor
6,226 Views
Registered: ‎05-29-2015

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Thanks Deepika. What about point number 5? The LED display driver is not instantiated in the VHDL top module. It would be helpful if points 4 and 5 are solved in the future releases.

0 Kudos
Xilinx Employee
Xilinx Employee
6,224 Views
Registered: ‎09-20-2012

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Hi @avinash200

 

Did you properly follow the below steps?

 

Capture.PNG

 

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Visitor avinash200
Visitor
6,220 Views
Registered: ‎05-29-2015

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Yes, I have followed this procedure. In the screenshot given, you will notice that there is an example_top.v in this directory, which replaces the default verilog top module in the example design, and instantiates the led_driver module. There is no replacement for the example_top.vhd which gets loaded with the default example design.

0 Kudos
Xilinx Employee
Xilinx Employee
6,215 Views
Registered: ‎09-20-2012

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Hi,

 

The language of top file depends on your project settings. You need to set the target language to Verilog in project settings so that verilog ip files are generated.

 

Does that help?

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Xilinx Employee
Xilinx Employee
11,067 Views
Registered: ‎07-11-2011

Re: Bugs and issues with MiG on Vivado 2014.4 and Windows 8.1

Jump to solution

Hi,

 

I do not think modified board design files will be provied for VHDL, if you wnat to test the board with VHDL then, go for new project, add MIG IP, and go with verify xdc and update deisgn and pin out pin out option in MIG, then import xdc and prj from the provided zip files.

If you need LED driver then you may need to instantiate it on your own vhdl tpp level file, but it is just needed for extensive testing and is not mandatory. You can use ILA to monitor init_calib_done and error siganls.

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos