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k@123
Visitor
Visitor
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Registered: ‎11-21-2016

CAN ANY ONE HELP ME

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I WANT TO CHECK DUC/DDC IP WORKING , SO HELP ME IN DESIGNING BLOCK DESIGN OF DUC/DDC USING ZYNQ7 FPGA

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balkris
Xilinx Employee
Xilinx Employee
6,019 Views
Registered: ‎08-01-2008

please generate the core from IP catalog . You can use demo testbench to simulate the core. Let me know if you stuck somewhere

 

check these document as well

 

https://www.xilinx.com/support/documentation/ip_documentation/duc_ddc_compiler/v3_0/pg147-duc-ddc-compiler.pdf
https://www.xilinx.com/support/documentation/application_notes/xapp1113.pdf

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
6,020 Views
Registered: ‎08-01-2008

please generate the core from IP catalog . You can use demo testbench to simulate the core. Let me know if you stuck somewhere

 

check these document as well

 

https://www.xilinx.com/support/documentation/ip_documentation/duc_ddc_compiler/v3_0/pg147-duc-ddc-compiler.pdf
https://www.xilinx.com/support/documentation/application_notes/xapp1113.pdf

Thanks and Regards
Balkrishan
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k@123
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Registered: ‎11-21-2016

i m using vivado 15.1 is it avalible if so,where do i find demo test bench 

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balkris
Xilinx Employee
Xilinx Employee
3,144 Views
Registered: ‎08-01-2008
Demo test bench will generate with core .
Thanks and Regards
Balkrishan
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